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TABLE OF CONTENTS
A NATIONAL SEMICONDUCTOR FAMILY OF ANALOG-TO-DIGITAL (A/D) CONVERTERS
A NATIONAL SEMICONDUCTOR FAMILY OF DIGITAL-TO-ANALOG (D/A) CONVERTERS
The AD7111 is a multiplying digital-to-analog (D/A) converter which can attenuate an analog signal by 88.5dB--in 0.375dB steps. It is controlled by 8 data lines and latching inputs. Its frequency range is said to be from DC to several hundred kHz (depending on an external op-amp, which it requires). It's quite the thing for controlling audio levels. Rather pricey, though; the AD7111K is about $30, and its "more accurate" counterpart, the AD7111L, is about $38.
This is said to be an "R-2R" D/A converter; the resistive ladder contains resistors of value R, and switched resistors of value 2 times R. The analog signal goes through sixteen resistors of value R, then through a resistor of 2R to ground. Each junction in the series string, including the beginning and end of the string, goes through 2R to the arm of a double-throw switch. One contact of each switch is grounded; the other contact of each goes to a bus labeled "I Out."
"I Out" goes to the inverting input of an op-amp; there is a feedback resistor from the op-amp's output to this inverting input. The non-inverting input is at some bias point, possibly at signal ground. This op-amp is not "on-board," but must be connected externally.
They provide an on-board feedback resistor, which one could ignore. Presumably, they put it there so that the designer can count on a value that roughly matches other on-board resistors in the system. The way they state it, "The AD7111 accuracy is specified and tested using only the internal feedback resistor."
The literature does recommend that a small-value resistor to boost the gain (for the 7111L, 180 ohms; for the K version, 270 ohms) be put in series with the internal feedback pin, and that the input resistance be trimmed by a 1K series rheostat. (This "trimming" of the gain is unimportant unless precise calibration of circuit gain is required.)
They recommend a good op-amp for critical applications; leakage currents at high attenuation levels can cause a significant DC offset on the output of the circuit. Therefore, they recommend that op-amps with less than 10 nanoamps of input bias current, and having less than 50 microvolts of input offset, be used. Output offset is most critical in DC applications, but if it is bad enough, audible "thumps" will occur when changing gain in AC-coupled systems.
Two component op-amps are mentioned in their literature: They suggest their AD711 without compensation, or their OP275 (with a 47pF capacitor across the feedback resistor).
The output resistance of the current source, I Out, varies with the input code; it can be anywhere from 0.8R to 2R. R is typically 11K.
The output capacitance, due to the N-channel switches, also varies with input code--ranging from 60pF to 185pF. These capacitances give rise to the feedthrough "glitches" mentioned in the definitions.
Logic in the chip translates the 8 bits into a 17-bit word. This is how they achieve multiplication (necessary to achieve the logarithmic response).
The "transfer function" is: V Out equals minus V in times 10 to the exponent of minus 0.375N over 20; or, attenuation in dB equals 0.375 times N, where "N" is the input code in decimal form--that number which is latched in the address lines.
Only numbers 0 through 239 (1110,1111) establish a gain. For an input of 240 (1111,0000) to 255, the output is zero; the chip "mutes" (which is a useful feature).
For an input of all 0's, there is no attenuation. For an input of 1110,1111, the attenuation is 88.5dB.
As explained in definitions below, "monotonicity," the expected change in gain with increments of N, is affected by the number of resistors involved with the digital-to-analog (D/A) conversion. Thus, in the commercial-grade devices, an increment in the binary input code could result in an increase in gain, rather than the expected attenuation (see definitions below).
"Positive logic" is used to impress a binary number on the data lines--plus 5V is logic 1. The "NOT Chip Select" must be low to enable the device. The "NOT Write" pin, on its positive transition, latches information on the data lines and starts the conversion; the time taken for data to propagate through the decoder is called the "refresh time."
Definitions (Special Terminology)
Resolution: This is the nominal analog response when moving between adjacent binary codes.
Monotonic: A D/A device is Monotonic if the change in gain, from one binary number to the next, is either zero or in the expected direction. For example, as you go from 0001,1111 on the data lines to 0010,0000, a lot of resistors of the D/A network are involved; the combined error of resistor tolerances could add up to an unexpected change of gain in the wrong direction (hopefully for only occasional binary increments).
(Note: High attenuation levels are specified with less accuracy than low attenuation levels, for the above reason.)
Digital-to-Analog Glitch Impulse: The "glitch" is the charge injected into the analog output from a change of state of the digital inputs. The area under the impulse is specified in either amp-seconds or volt-seconds (amp-seconds here, because the output is a current source).
Leakage Current:For these devices, "leakage current" (significant in DC applications and at high attenuation levels) is defined as that sourced by the I Out pin when the chip is mute (all 1's on the inputs, for example). It varies widely with temperature; typically, it might go from 0.01 nanoamps at 5 dg.C. to 100 nanoamps at 125 dg.C.
- Analog Ground to Digital Ground--0 to VDD.
- Digital Ground to Analog Ground--0 to VDD. (Usually connected together, presumably these pins can be different by as much as VDD in either polarity.)
- Absolute Maximum VDD--7V; intended to operate from a single 5V supply.
- Digital Input Voltage Range (with respect to "digital ground")--minus 0.3V to VDD plus 0.3V.
- Minimum Logic High--2.4V.
- Maximum Logic Low--0.8V.
- Minimum "Write Pulse" Width--350 nanoseconds.
- "Data Valid" to Write Setup Time--175 nanoseconds, minimum.
- "Data Valid" to Write Hold Time--10 nanoseconds, minimum.
- "Refresh time"--3 microseconds, minimum.
- Voltage Limits that can be Imposed on the Output Current Pin (with respect to analog ground)--minus 0.3V to VDD.
- Absolute V In to Analog Ground--plus/minus 35V; swings of plus/minus 25V are mentioned elsewhere in the literature.
- Analog Input Resistance for the AD7111K--minimum 7K, typically 11K, maximum 18K.
- Input Resistance for the AD7111L--Minimum 9K, typically 11K, maximum 15K
- On-Board Feedback Resistor for the AD7111K--Minimum 7.3K, typically 11.5K, maximum 18.8K.
- On-Board Feedback Resistor on the AD7111L--Minimum 9.3K, typically 11.5K, maximum 15.7K.
- Operating Temperature Range (of the "commercial-grade" with suffixes of K or L)--0 to 70 dg.C.
- Monotonicity for the AD7111K--Guaranteed to be monotonic for 0.375dB steps up to 48dB; guaranteed to be monotonic for 0.750dB steps up to 72dB.
- Monotonicity for the AD7111L--Monotonic for 0.375dB steps up to 54dB; monotonic for 0.750dB steps up to 72dB.
- Pin 2--Analog Ground
- Pin 3--Digital Ground
- Pin 14--VDD, 5V
- Pins 11, 10, 9, 8, 7, 6, 5, 4--Data Inputs 0 through 7 (least-significant at pin 11)
- Pin 12--NOT Chip Select (low to enable)
- Pin 13--NOT Write(positive transition latches data info and starts conversion)
- Pin 15--Analog Input ("V In")
- Pin 16--On-Board Feedback Resistor
- Pin 1--"I Out" (a current source)
Pins 2 and 3 of the AD7111 are grounded. Pin 14 goes to the 5V line.
A single op-amp has pin 4 going to minus 15V; pin 7 goes to plus 15V. Pin 3, the non-inverting input, is grounded. Pin 2, the inverting input, goes to "I Out" (pin 1) of the 7111. Pin 6 of the op-amp, the output, goes through an optional 270 ohms to pin 16, the internal "feedback" resistor that runs between pin 16 and the "I Out" (pin 1 of the 7111).
Pin 15, the analog input, goes through a 1K trim pot, connected as a rheostat, to the signal source.
To enable the chip, pin 12 is grounded. Pin 13 is manipulated to initiate data conversion (on the positive transition).
Alternatively, they are kind enough to tell us that the voltage on I Out can be anywhere from minus 0.3V to VDD (5V). Thus, we could get rid of the dual supply (if we are content with a limited voltage swing of the op-amp). By biasing the non-inverting input of the op-amp, we will establish the "virtual ground" at the inverting input just below 5V.
Pin 4 of the op-amp is grounded; pin 7 goes to plus 9V. Between 9V and ground are two 47K resistors in series; the junction of these resistors is bypassed to ground by 10uF (negative of the cap at ground). Pin 3 of the op-amp goes to the junction of the 47K resistors, which puts the virtual ground on pin 2 at 4.5V.
Since I would rarely care about the precise gain of the system, I'll forego the input rheostat and couple this circuit to the source with perhaps 10uF (the negative end of this cap probably going to the source). The input impedance is "R"--which will vary from device to device.
These are 20-pin chips capable of converting an analog voltage to a digital quantity appearing on eight data outputs (the 8-bit number ranging from 0 through 255). Their "differential inputs," together with a pin by which the allowable input range can be selected, gives you the flexibility to adjust the offset and range over which the full resolution can be achieved.
Conversion time can be 100 microseconds (depending on selection of clock speed). They are capable of self-clocking; however, in some applications you may wish to derive the clock signal from a microcontroller, and an external clock signal can be used.
They are of the "successive-approximation" type. In fact, the heart of the circuit is a digital-to-analog (D/A) converter operating in the feedback loop of a comparator. Switches operating on a ladder network are successively set so that the voltage on an output from the ladder arrangement approximately equals the voltage between the differential input terminals. (The circuit of the ladder network is not shown in the literature.)
After 64 clock cycles, the "positions" of the switches are relayed to output latches, at which point, an "interrupt" pin makes a high-to-low transition which signals other circuitry that the data lines can then be read (once they are taken out of the tristate condition).
Conversion is initiated with a high-to-low transition of the "NOT Write" pin. It takes a short time to reset internal workings of the chip; then 64 clock pulses later, the conversion is complete. The conversion can be interrupted and restarted at any time with another fall of the "NOT Write" pin.
In the "free-running" hookup (not to be equated with running of the internal clock), the Interrupt output is connected to the "NOT Write" input. Every time the Interrupt goes low to say that a conversion is done, a new conversion is initiated. There is a quirk to this arrangement though; the first cycle must be started manually by grounding the "NOT Write" pin with a pushbutton or some such.
The "span" of definable input voltages is determined by the voltage on pin 9. Pin 9 goes to a resistor network inside the chip which is involved in the "feedback" D/A converter; pin 9 goes through a resistor to pin 20, as well as going through a resistor to a ladder network with switches to ground. This "span" (defined input range) is twice the voltage appearing on pin 9.
Externally imposing a voltage on pin 9 changes the gain of the analog-to-digital (A/D) conversion. With no connection to pin 9 and with a supply of 5 volts, the internal network sets this voltage to 2.5V, and the span of the input voltage will be 5 volts.
The analog inputs are differential; i.e., the voltage range need not be based at 0 volts. Common-mode signals--noise or other signals common to both inputs--are ignored. By lifting the minus input above ground, you can shift the level of defined inputs.
Let us now suppose that we wish the A/D conversion to respond to an input signal whose range spans 3 volts, and that we wish to define "0" as 0.5V--conversion from 0000,0000 to 1111,1111 will take place over an input range of 0.5V to 3.5V. Imposing a voltage of 1.5V on pin 9 will set the span to 3 volts; putting 0.5V on pin 7 will shift the level by half a volt. (Remember that the impedance on pin 9 can be low, 2.5K for all but the 0804, whose impedance on pin 9 can be as low as 750 ohms. Thus, the external source must be low-impedance. The pin 7 input is high-impedance.)
For example, if the desired range of voltage is 0.5V to 3.5V, tying pin 7 (the minus input) to 0.5V will direct the chip to generate all 0's for an input of 1/2-volt.
The device has an on-board clock, the sort made from a Schmitt trigger. This requires a resistor (10K is shown) between pins 19, a Schmitt trigger output, and pin 4, its input; a capacitor (150pF is shown) goes from pin 4 to ground. The clock frequency is approximately 1 over 1.1 RC. They caution you not to heavily load pin 19 externally. With a load of 360uA, the logic zero out will be a maximum of 0.4V; a logic 1 will be 2.4V minimum. They further caution against capacitive loading of pin 19.
Being a Schmitt trigger, the clock input thresholds are of interest. Worst-case figures show that a positive-going pulse must exceed 3.5V, and the negative transition must go below 1.5V. Thus, the maximum hysteresis is 2 volts.
The outputs are compatible with both CMOS and TTL drive levels. The outputs can sink more current than they can source. If they are asked to source a current of 360 microamps, their logic "1" could be a minimum of 2.4V. However, so that they can drive two low-power or one Schotkey TTL input, they can sink more than 1.6mA and provide a sufficiently low logic "0."
These chips have three digital control inputs: "NOT Chip Select," "NOT Write," and "NOT Read." The "NOT Chip Select" and "NOT Read" pins are related in that they put the outputs into the tristate (high-impedance) mode (they go to inputs of a common AND gate). They differ in that the "NOT Chip Select" also goes to an AND gate whose other input is the "NOT Write" pin. Thus, the "NOT Chip Select," when at logic high, causes the chip to ignore any signals on the other two.
A microcontroller shares data lines, as well as sharing "read" and "write" lines with other devices, and a way must be provided by which any such device can know, "These start and read pulses are not for you."
To make interfacing easy, these logic inputs can be taken to 15 volts, even though the chip supply is 5V. The maximum logic low is 0.8V; the minimum logic high is 2.5V.
The accuracy varies with the choice of chips in the series. The tolerances of the resistors in the ladder of the internal D/A converter are the key. Besides errors stemming from mismatched resistors in the ladder, the sampling resistor, whose IR drop is compared with the input, can have an overall effect on what is called the "total unadjusted error" (meaning that the internal reference voltage is in error). If an external reference is imposed on pin 9, they speak of the "total adjusted error" (the degree of precision after the reference pin is forced to be where you want it).
The ADC0801 is the best, said to afford a "total error" of one-quarter least-significant bit (LSB).
Power requirements (operates on single supply):
- VCC Absolute Maximum--6.5V
- Typical Operating VCC--4.5V to 5.5V
- Current Drain (presumably with no load on outputs)--1.8mA maximum for all but the 0804 which can draw 2.5mA maximum
- Data Output Logic 0 (sinking 1.6mA)--0.4V maximum
- "Interrupt" Output Logic 0 (with 1mA load)--0.4mA maximum
- Logic 1 for All Outputs (with 360uA load)--2.4V minimum
- Absolute Extremes of Logic Control Voltages--Minus 0.3V to 18V
- Input Logic 0--Less then 0.8V
- Input Logic 1--2.5V minimum, but can be taken to 15V
Clock Schmitt Trigger Specs:
- Absolute Limits for Clock Input--Minus 0.3V to VCC plus 0.3V
- Minimum Threshold for Logic 0--1.5V
- Maximum Threshold for Logic 1--3.5V
- Schmitt Trigger Output Logic 0 (with 360uA load)--maximum 0.4V
- Schmitt Trigger Output Logic 1 (with 360uA load)--Minimum 2.4V (this pin 19 not to be heavily loaded)
External Reference Pin:
- Impedance of Pin 9 (VREF over 2)--8K typical, 2.5K minimum(for the 0801, 0802, 0803, and 0805)
- Impedance of Pin 9 (on the 0804)--1.1K typical, 750 ohms minimum
Plus and Minus V In pins:
- Analog Input Voltage Range--Ground Minus 0.05 to VCC plus 0.05
- ADC0801 Total Adjusted Error--plus/minus 1/4 LSB
- ADC0802 Total Unadjusted Error--plus/minus 1/2 LSB
- ADC0803 Total Adjusted Error--plus/minus 1/2 LSB
- ADC0804 Total Unadjusted Error--plus/minus 1 LSB
- ADC0805 (with no connection to pin 9)--plus/minus 1 LSB
- Sensitivity to Power Supply Variations (plus/minus 10%)--Typically 1/16 LSB, maximum 1/8 LSB
- Conversion Time in Clock Periods--Between 66 and 73 periods of the clock, hence
- Conversion Time for 640kHz Clock--Between 103 and 114 microseconds
- Recommended Clock Frequencies--100kHz minimum, 640kHz typical, 1460kHz maximum (f equals 1 over 1.1 R times C)
- Conversion Rate of Free-Running Mode (for 640kHz)--Between 8770 and 9708 conversions per second
- Required Pulse Width of the "NOT Write" Input Signal (with "NOT Chip Select" low)--100 nanoseconds
- Access Time (from falling edge on the "NOT Read" input to getting valid data)--Maximum 200 nanoseconds
- Time to Achieve Tristate Condition (following rising edge of "NOT Read")--Maximum 200 nanoseconds
- Time for Reset of the "NOT Interrupt" Output (following falling edge of "NOT Write" or "NOT Read")--Maximum 450 nanoseconds
ADC0801, ADC0802, ADC0803, ADC0804, and ADC0805
Power Supply and Reference Connections:
- Pin 20--VCC (this voltage also being called "VREF")
- Pin 8--Analog Ground
- Pin 10--Digital Ground
- Pin 9--VREF over 2 (resting at one-half VCC unless otherwise imposed on)
- Analog Input Pins:
- Pin 6--V IN plus
- Pin 7--V IN minus
Digital Inputs and Clock:
- Pin 4--Clock In
- Pin 19--Clock R (a resistor from 19 to 4, see text)
- Pin 1--NOT Chip Select (high puts outputs into tristate)
- Pin 2--NOT Read (high puts outputs into tristate)
- Pin 3--NOT Write (also might be termed the "start" input)
- Pin 5--NOT Interrupt
- Pin 18--Data Out 0
- Pin 17--Data Out 1
- Pin 16--Data Out 2
- Pin 15--Data Out 3
- Pin 14--Data Out 4
- Pin 13--Data Out 5
- Pin 12--Data Out 6
- Pin 11--Data Out 7
This is the "free-running" hookup; it's fairly obvious how you might operate all its inputs from other circuitry. Moreover, let us begin with the unmodified scale factor; i.e., 0 through 5V will give us binary numbers of 0000,0000 through 1111,1111 (0 through 255).
Both analog and digital ground pins, pins 8 and 10, are grounded. Pin 20 goes to the 5V VCC. If we always want to see the outputs as they come up, both "NOT Chip Select" and "NOT Read" are grounded.
We connect it in the "free-running" operation by tying the "Interrupt" output, pin 5, to the "NOT Write" or "start" input. To get it started, a normally open pushbutton goes from pin 3 to ground. (The data sheet proclaims this an all-right thing to do. Elegance would have us run pin 5 through a 47K resistor to pin 3, but what the heck.)
To utilize the internal clock, pin 19, the output of the Schmitt trigger, goes through 10K to pin 4, with pin 4 going through 150pF to ground.
The "Minus V In" terminal, pin 7, is grounded. The analog input is pin 6, the "Plus V In" terminal.
Now, let us propose a different scale factor; if we define the range to be from 0 to 2.55V, the least-significant bit would change for each 0.01V. To accomplish this, we put a low-impedance voltage source on pin 9. The value of this source is 1.275V, half of 2.55V.
Simple enough. But now suppose we are interfacing with some upside-down circuit that wants to give us our 2.55 volts with its "base line" at 5 volts; i.e., we want 5V input to give us all zeros and 3.45V to give us all ones. We can tie the plus input, pin 6, to pin 20, and put our signal on the minus input.
These 20-pin chips convert a binary number impressed on eight data inputs to an analog current which is proportional to the binary number (ranging from 0 through 255). They are said to be of the "R-2R" type D/A converters; a resistive ladder contains resistors of value R, and switched resistors of value 2 times R. The ladder is powered by an external voltage reference. CMOS switches connect resistors to either of two buses, labeled "I Out 1" and "I Out 2."
"I Out 1" is at maximum when data inputs are all at logic 1, and it is 0 (except for a small amount of leakage) with all 0's on the inputs. "I Out 2" is a maximum for an input of all 0's, and approaches zero as a count of all 1's is approached.
An op-amp converts the current source to an analog voltage output. This op-amp is not "on-board," but must be connected externally. A connection on the converter chips goes to a feedback resistor which matches the other resistors in the ladder. You should use their feedback resistor and not an external one of your own, since the ohmic values from chip to chip are not actually known.
In the most common setup, "I Out 1" goes to the inverting input of an op-amp. The op-amp's non-inverting input and "I Out 2" of the converter are grounded. The output of the op-amp goes to the "R Feedback" pin on the converter chip.
When connected as described above, the output of the op-amp will go negative in proportion to the input code, with its maximum excursion dependent on the input reference. Note that the total output swing is V-Ref minus the increment of one least-significant bit. In other words, all 1's on the inputs translates into minus 255/256 times the voltage reference. If a 10V reference is used, the output will go from 0V to minus 9.961V. By adjusting the reference a little high, you can force 255 to give you an output of 10V, at the same time, compensating for any overall "gain error."
It seems that good design practice is to keep the "virtual ground" of the op-amp at ground, not imposing an offset on its non-inverting input. This is so, because there is a "linearity error" that comes about when the current-source outputs are at a different potential from one of their ground terminals, pin 10. This error will be the offset voltage with respect to pin 10 divided by 3 times the reference voltage. The literature gives the following example:
If the output pins differ from pin 10 by 9 millivolts (0.009V) and the reference voltage is 10 volts, the error in linearity will be: 0.009 over 30 equals 0.0003, which is 0.03%.National defines "linearity error" as the maximum deviation of a straight line through the "end points" of the output swing; they call this the "end-point test." Other manufacturers may use a "best straight-line test" -- the error deviating from a line drawn to match as many of the 256 points as possible.
While they can be wired in a "flow-through" configuration (the output reflecting all activity on the data-input lines), these converters are "double-buffered"; there are two sets of latches so that the output signal can be updated when desired. Like their A/D relatives (see the previous article), "NOT Chip Select," "NOT Write" and "Input Enable" pins allow a microprocessor to direct the conversion activities.
There is a set of "input latches" which are controlled by the "Input Latch Enable" (high to enable). Bringing this "Enable" high, and the "NOT Chip Select" low, enables the "NOT Write 1" input; bringing the "NOT Write 1" low loads the input data into this first set of latches; bringing "NOT Write 1" high holds data there.
The second set of latches is called the "DAC register"; these are loaded with the operation of the "NOT Write 2" which, in turn, is "enabled" by the "NOT Transfer" pin (brought low to enable the transfer). With the "NOT Transfer" pin held low, bringing "NOT Write 2" low transfers data from the input latches to these second latches (the DAC Register); bringing "NOT Write 2" high holds the data there.
As for the circuitry, the DAC Register's enable function is controlled by a 2-input AND gate; one input is the "NOT Write 2" pin, and the other is "NOT Transfer." For operation of the input latches, the "NOT Chip Select" and the "NOT Write 1" are inputs of an AND gate, while the output of this gate is AND'ed with the "Input Latch Enable" terminal.
For "flow-through" applications, the "Input Latch Enable" is tied high, and all other control inputs are tied low.
Single-buffer operation is the most common usage; a microprocessor would direct an update of converters one at a time. Double-buffer operation allows inputs to be noted at different times, and then several converters can be directed -- with a single strobe signal -- to present their updated outputs simultaneously.
In single-buffer operation, one of the buffers is set up to allow continuous flow-through of data. The other set of latches is used to hold data as desired. The literature mentions, and this stands to reason, that "digital signal feed-through" is minimized if the DAC Register is chosen for flow-through ("NOT Transfer" and "NOT Write 2" tied low), and the input latches are operated by strobing "NOT Write 1" low ("Input Latch Enable" must be high and "NOT Chip Select" must be low for operation).
Logic inputs are compatible with both CMOS logic and TTL. The literature warns, however, that if pin 3, one of the ground terminals, is at some potential other than pin 10, logic levels will be shifted. (They do not explain why there are two ground pins, nor do they speak technically of the differences.)
The external reference can be of either polarity and can be as much as 10 volts.
The literature makes a point that these converters can be used for "4-quadrant multiplication." In a manner of speaking, the output current is a product of the value of the binary input and the voltage on the reference pin (thinking of the "reference" pin as an analog input). The analog input (the reference) can be of either polarity, and you can arbitrarily treat 1000,0000 as a baseline of zero (thus affording positive and negative numbers as inputs). In so doing, the highest-order bit becomes a "sign indicator" -- plus or minus. (In the specifications, there is listed a "feed-through error"; V-Ref is a sinusoid, and the data inputs are held at zero.)
By adding another op-amp connected as described below, we can generate a bipolar output and perform a 4-quadrant multiplication.
A "negative binary number" (127 or less), multiplied by a negative voltage on the reference pin, would yield a positive output. A positive binary input (128 or greater) and a negative reference, or a positive reference and a binary number of 127 or less, would both yield a negative output swing. Two positive inputs, a binary number of 128 or greater and a positive voltage on the reference pin, would yield a positive output.
[I am having a nightmare; I'm in engineering school again. I haven't been to class very often; I can't quite remember the room number. The mid-term test is tomorrow? Oh help!!!] The second op-amp circuit should be connected as follows: The non-inverting input is grounded. A feedback resistor of value 2R goes from the output to the inverting input of the op-amp. An input resistor of value R goes from the output of the first op-amp (the output of the basic D/A circuit) to the inverting input. A second input resistor of value 2R goes from V-Ref (pin 8) to the inverting input.
- VCC--4.75V to 15V, 17V absolute maximum
- Supply Current--2mA (excluding current drain from referent drain)
- Power Supply Sensitivity--For 4.5-5.5 volt range, 0.015% per volt; for 14.5-15.5 volt range, 0.0025% per volt
- Output Leakage (for all zeros on inputs)--100 nanoamps
- Feed-Through Error (with data inputs held at zero and with a 100kHz sinusoid of 20V peak-to-peak on the V-reference pin)--3mV peak-to-peak
- Current Settling Time--1 microsecond (the time taken for the output current to be within plus/minus one-half the value of the least-significant bit)
- Logic Inputs--0 to VCC
- Logic Low--0.8V maximum
- Logic High--2V minimum
- Reference Input--plus/minus 25V (plus/minus 10V or less in typical operation)
- Reference Input Impedance--Minimum 10K
Accuracy (for VCC plus/minus 5%):
- Maximum "Linearity Error--DAC08330LCN, 0.05%; DAC08331LCN, 0.1%; DAC0832LCN, 0.2%
- Differential Nonlinearity--DAC0830LCN, 0.1%; DAC0831LCN, 0.2%; DAC0832LCN, 0.4% (this being the deviation from the ideal as you step between adjacent input codes)
- Gain Error--plus/minus 1% full-scale (for all)
- Gain Error vs. Temperature--0.0006% per Dg.C. (for all)
Timing (a 5V supply is the worst case):
- Minimum Write and Transfer Pulse Width--900 nanoseconds with 5V supply; 320 ns at 15V
- Minimum Data Setup Time--900 ns with 5V supply; 320 ns at 15V
- Data Hold Time--50 ns with 5V supply; 30 ns at 15V
- Minimum "Control Setup Time"--1100 ns with 5V supply; 320 ns at 15V
- Minimum "Control Hold Time"--10 ns (for VCC of 12V to 15V)
Pin Assignments for DAC0830LCN, DAC0831LCN, and DAC0832LCN
(Chips with other suffixes may have the same pin-outs; these are 20-pin DIP.)
- Pins 3 and 10--Ground (somehow not equivalent, so ground them both)
- Pin 20--VCC
- Pin 19--Input Latch Enable
- Pin 1--NOT Chip Select
- Pin 2--NOT Write 1
- Pin 17--NOT Transfer
- Pin 18--NOT Write 2
- Pin 7--Binary Input 0 (least-significant bit)
- Pin 6--Binary Input 1
- Pin 5--Binary Input 2
- Pin 4--Binary Input 3
- Pin 16--Binary Input 4
- Pin 15--Binary Input 5
- Pin 14--Binary Input 6
- Pin 13--Binary Input 7 (most-significant bit)
- Pin 8--V Reference (or can serve as an analog input for multiplication)
- Pin 9--R Feedback (goes to the output of the op-amp)
- Pin 11--I Out 1
- Pin 12--I Out 2
A Ramp Generator
An 8-bit counter is fabricated, clocked perhaps from a variable-frequency source. The eight outputs from the counter go to the data inputs of a DAC0832LCN (pins 7, 6, 5, 4, 16, 15, 14, and 13, in ascending order).
Pins 3 and 10 are ground; also grounded are control pins 1, 2, 17, and 18. Pin 19, when low, disables the input latches, so we will connect it through 47K to VCC, and also put it through a "standby switch" to ground.
The power supply is a dual one -- plus and minus 15 volts. The junction of the supplies is grounded. Pin 20 of the converter goes to plus 15V.
An op-amp -- shall we choose a dual one such as an LM358 -- has pin 4 going to minus 15V and pin 8 going to plus 15V. Pin 3, the non-inverting input, is grounded. Also grounded is pin 12 of the converter, "I Out 2." Pin 2 of the 358 goes to "I Out 1," pin 11 of the converter. Pin one of the 358, the output, goes to pin 9, the converter's internal feedback resistor.
So that we can control the amplitude of the ramp, a variable supply will feed the V-Ref terminal, pin 8. A negative reference will give us a positive-going ramp.
The bottom of a 10K amplitude control is grounded. The top of the control, its clockwise end, goes through 4.7K to minus 15V. The arm of this control goes to pin 5 of the 358. Pins 6 and 7 of the 358 are tied together and go to pin 8 of the converter.
Well, it's been a while. No one realizes that more than me. I squirm in my sleep so often that they have made waterbeds illegal in San Francisco; it seems I was affecting the tides.
However, here we are, back on line, and there is fun afoot.
What's all this A/D-D/A conversion about?
Two things have held us back from delving into microprocessor theory:
The main one is that, while the chips themselves have been cheap for nearly two decades, the tools for the designer, known as "development systems," were breath-takingly expensive. Now, however, we can get attachments for our home computers that will allow us to write firmware and emulate circuits with the mere sacrifice of new clothes and shoes for the children.
The other necessity is laying down background material: What do you do with a microprocessor and all of its "input/output" data lines? Converters, such as those described in this issue, are the ears and mouths of microcontroller circuits, to a large extent. These, along with stepper-motor drivers, high-current open-collector device drivers, sensors (such as the position sensors and pressure transducers we have described), constitute ways of sensing and acting out worldly tasks.
We're getting closer to adopting computers as components in the Tinkertoy Set of projects to come.
Happy New Day, everybody.