The Smith-Kettlewell Technical File

A Quarterly Publication of The Smith-Kettlewell Eye Research Institute’s Rehabilitation Engineering Research Center

William Gerrey, Editor

Issue: sktf-Summer-1981

Original support provided by: The Smith-Kettlewell Eye Research Institute and the National Institute on Disability and Rehabilitation Research

Note: This archive is provided as a historical resource. Details regarding products, suppliers, and other contact information are original and may be outdated.

Questions about this archive can be sent to


Gabbing About Gates

Inside Gates


Counting in Base Two

Technical Innovations Bulletin

Editor's Corner


[Editor's Note--Probably to the detriment of this fine treatise, the editor has seen fit to complicate things by inserting supplemental material into the text. These supplements will be indicated by enclosing them in brackets. The beginner might well skip over these aside comments at first reading, so that the feel of these difficult concepts can be captured as Mr.Plumlee intended.]

This article should answer a request from several readers asking for basic information on digital logic. We are going to focus our attention on a brief explanation of inverters and 2-input gates. While this article may, be viewed by some as an over-simplified discussion of the subject, it is a beginning treatise; we cannot squeeze a whole textbook into one article. Rather, my goal in writing this paper is to give you enough information to begin using these "basic logic blocks" (inverters and gates) in digital circuits.

In binary logic,only two conditions or "states" are possible -- yes,no.

These two states can be expressed as yes,no; high,low; E,L; 1,0; VCC,0 volts. A logic 1 means yes, and appears as VCC (the supply voltage) on the terminal pin of the device. A logic 0 means no, and appears as 0 volts.

Perhaps you have heard of OR, NOR, AND, and NAND gates. We can describe their operation in terms of logic operations that you perform in everyday life. I think you will shortly see that there are more "gates" in your life than you realize.

Logic Operations

Let us consider everyday situations, which illustrate four "logic operations", operations which we symbolically refer to by the words "NOT", "AND", "OR", and "ONLY".


Consider making tentative plans for a family dinner outing. "If you come home before 7:00 (input=1), I will NOT cook supper (output=O)." Conversely, the implication is that "if you do NOT come home by 7: 00 (input=0)" I will cook supper (output=1)."

The mechanism of inversion is used in automatic outdoor lighting systems. When sunlight shines on a sensor, the floodlights being controlled are shut off. Put another way, when the sun shines on the sensor (input =1) 1. the floodlights go NOT on (output=0).

Since we have only two "states" possible, the inverter provides at its output the state that you do NOT have at the input (out= -in), a phase shift of 180 degrees.


Consider the cashing of a check which is made out to both Robert and Sharon Jones. This check can be cashed (out=1), if both Robert AND Sharon sign it (A=1 AND B=1). If neither of them sign it (A AND B = 0), the check is invalid (out=0). If Robert signs (A=1), AND Sharon does NOT (B=0), the check is no good (out=0). If Robert does NOT sign AND Sharon does (A=0 AND B=1), the check, is no good (out=0). Thus, it takes both signatures (A=1 AND B=1) for the check to be cashed. The AND gate is the electronic implementation of this principle. If both inputs = 1, the output = 1.


If the Jones's were to establish a joint checking account, either Robert OR Sharon alone could write a valid check (out=1 for A=1 OR B=1). In the unlikely event that both of them would choose to sign a check (both A AND B =1), the check would still be valid (out=1); the second signature does nothing to enhance the validity of the check. Once you achieve "validation" by raising one input to a logic 1, the state of the other input is simply ignored. The OR gate is the electronic implementation of this principle. This logic is sometimes called "AND/OR", since it allows the output to be logic 1 if both inputs are logic 1.

Exclusive OR

We may have need for an OR function with exclusivity (exclusive OR). If you want to make a logic OR decision, but you want the output to respond to ONLY ONE input at a time you need an Exclusive OR. Consider the example of sitting at a lunch counter, whose menu lists a "special" called the "Ham Sandwich Platter". On this special "Platter", you get a choice of baked beans or french fries. There is an exclusive OR gate built into the system-you can't have both beans AND fries on the special. If you order baked beans (A=1) OR french fries (B=1), you have a valid order (out=1).

If you say, "I don't want either beans OR fries" (both inputs at logic 0), or "I would like both beans AND fries" (both inputs at logic 1), you do not have a valid order for the special (out=0).

[For listing an input condition, we will adopt the notation of mathematicians-- Y=f(A,B). For example, the input situation on a gate, where A=1 and B=0 will be written (1,0).]

Another way of viewing this Exclusive OR gate is to say that in both cases, where the two inputs are equal, (0,0) and (1,1), the output will be logic 0. This device can thus be used to indicate when opposite levels appear at its inputs.

It is important to note here that the Exclusive OR does not decode (identify) which input is at a given logic level; it merely determines whether or not our order for the "Platter" is valid. The mind of a helpful waitress will, as it were, use other gates to decode (identify) the four input states--two invalid (0,0) OR (1,1), and two valid (0,1) and (1,0). For (0,0), for instance, she might say, "you apparently want ONLY the sandwich; I'll make your order for that, and you will save 50 cents by not ordering the Platter. For (1,1) she might say, "you can ONLY have one choice with the Platter, but I will be happy to get the other one for you as a side order." The point to keep in mind here is that with an array of gates, you can make more than one logic decision off an input--one for validity of an input situation, and another to identify which alternative has been selected.


A "NAND" gate is an AND gate with an inverter as an output stage (to NOT the output). Similarly, a NOR gate is an OR gate with a NOT as the output stage. To predict the output under a given input condition (for a NAND or NOR), first determine what it would be if you had an AND or OR, then invert your answer to allow for the inversion that takes place at the output.

Understanding the schematic symbols for the NAND and NOR gates should bring this point home. Logic inversion is denoted by a circle. The NAND and NOR gates have a small circle drawn at their output to indicate logic inversion.

[The schematic symbol for an OR gate looks like a drawn outline of the end of a nice fat cigar, or, perhaps the end of your thumb (pointing to the right). The left end of the OR symbol is not flat; it has a concave or pushed-in left end. An Exclusive OR gate has two concave curves of different depths drawn across its left end. The AND gate, on the other hand, is half an oval (perhaps the pointed end of an egg) with a flat left end. A line coming straight out from the right end of these symbols is the output line. Parallel lines butting up against their left end are the inputs; a 2-input gate has two such lines. As mentioned in the text, NAND and NOR gates have a small circle drawn touching the outside of the right end of the gate symbols, with the output line coming off the far side of this circle.]

[The Truth Table]

[Functions of gates are tabulated in the following manner:]

AND Function (Y=f(A,B))






[Just for variety, we will use 1's and 0's in the following example:]

NAND Function


0 0 1

1 0 1

0 1 1

1 1 0


I have a tone from an oscillator, which I want to pass along to an amplifier in response to a positive signal from a control line. If the control line is grounded (at 0 volts), I want the tone to be interrupted. Just for devilment, I want a phase inversion between output and input. What kind of gate should I use?


Ignoring the phase shift for a moment, let's figure out how to gate the tone signal on and off, given a positive control pulse. As far as basic function is concerned, we have a choice between AND gates and OR gates. To utilize the function of such a gate, we will connect the control line to one input, and the signal to be gated to the other. The standby situation will have the control line grounded (input A=0).

Suppose we were to select an OR gate. Recall that we need only one input to go positive for the output to go positive. We quickly realize that, if A is at ground, the output is strictly under the control of the signal coming into B, hence the tone would be passed along to the amplifier. If the control line goes to logic 1, the output is locked at logic 1 without respect to the state of B, hence no tone is passed along to the amplifier. With an OR gate, therefore, our control works in the opposite way than was stipulated in the problem.

If we choose an AND gate, consider what happens when the control line is grounded (A=0). The output will never get to the logic 1 level; both inputs have to be high for the output to change state (out=1). The output is therefore locked at logic 0, for A=0, and no tone is passed by the gate. If the control line goes positive (A=1), we at least meet one of the conditions necessary to utilize the AND function. The other necessary condition is up to the B input, which carries the tone. When the B input=1, out=1, and when B=0, out=0 -- the tone is thus passed along to the amplifier. When the control line is positive, there is a tone. When the control line is grounded, the AND gate refuses to change state, and the tone is not present at the output.

What about the condition that the output and input must be 180 degrees out of phase? If we follow the AND gate with an inverter, we get the phase reversal stipulated. But a NAND gate is an AND gate with an inverter. Therefore, a NAND gate is the gate of choice to satisfy all conditions of the problem.

Remember that the OR or NOR gate is also useful in control applications, for you will often find it to your advantage to use an "active-low" control, and you may need the inversion of the NOR, depending on your specific application.


Describe the output of a 2input AND gate, if its 2 inputs are fed with square-waves A and B, and the frequency of A is 3B/2. The two signals are in phase; they start by going high together.


Well, I hear some of you saying, "you're going to go back on your word now and spring advanced math on us instead of everyday English." Not quite, I believe in the acronym KISS (Keep It Simple, Students).

We know that 3 cycles of A take as long as 2 cycles of B. We will examine a period of time exactly long enough for 3 cycles of A to occur. In 3 cycles of A, A will make 6 transitions, 3 positive and 3 negative in alternation (1,0,1,0,1,0). In the same time, 2 cycles of B will make 4 transitions, 2 positive and 2 negative. Thus, in this same period of time, we will examine 6 states of A, while we concurrently look at 4 states of B. Each transition takes 1/6th of the time period we are considering. Each transition of B takes 1/4th of the period. Putting these fraction in a form with a common denominator, we find that each transition of A takes 2/12ths of a period, and each transition of B takes 3/12ths of the period.

We shall write a chart accounting for the states of A and B at each 1/12th period interval. We will list the states of A on the first line (A--HHLLHHLLHHLL). Similarly, on the second line we will list the states of B. On the third line, we will number the 12 segments into which we have divided the complete period.

A--H H L L H H L L H H L L

B--H H H L L L H H H L L L

1 2 3 4 5 6 7 8 9 10 11 12

Applying the logic AND function, a fourth line can be derived listing the output states. Remember, the output will be low for all input conditions except A=H AND B=H. Your completed chart should look as follows:

A--H H L L H H L L H H L L

B--H H H L L L H H H L L L

1 2 3 4 5 6 7 8 9 10 11 12


If your chart does not look like the solution given above, let me help you a bit. Consider the numbered line as the "home" line and read up from it. The presence of an L in any column means the output cannot be high.

You could make the same chart for a NAND, a NOR, or an OR. You can tabulate more inputs, if you want. The common denominator establishes your "sampling rate", and it determines the number of entries in a line. In this way, you could describe the output of a gate having many inputs fed by square-waves of known relationship. Such an analysis would go far beyond what we need in this article, and would turn into mere busy work--I hate busy work.

What about Chips?

Now that we have a basic understanding about logic operations and how they can be used in electronics, what chips can we buy to do these operations? There are, of course, many gate configurations available, so we can only touch on a few of the simpler ones and give a few general ideas that hold for all of them.

You generally do not find only one gate on a chip. They are mostly dual, triple, or quad. What would you expect, if you picked up a dual 4-input NAND gate? If you answer that you expect to find 2 NAND gates, each having 4 inputs, you are right. What about a quad 2-input NOR gate? This package contains four NOR gates, each having 2 inputs.

These designations also help determine the minimum number of pins you expect to find on a chip. Take, for example, the quad 2-input NOR gate. NOR has nothing to do with pin counting--for the moment, we will ignore it. We know that the chip has four gates with 2 inputs each. Each gate must also have an output, giving us 3 connections per gate. 4 times 3 equals 12; we add one for VCC (the plus supply) and one for ground. Thus, we get 14 as the minimum number of pins.


If you could find such a chip, what minimum number of pins would you expect to find on a dual 8-input gate?


Each gate has 9, connections utilizing 18 pins. As before, we need 1 pin for VCC and 1 for ground, bringing the total up to 20. Such a chip would need at least 20 pins; and it may very likely have 24 pins, with 4 of them being marked "NC" (No Connection).

"Why worry about the number of pins per chip? Isn't that the manufacturer's problem?" It is, but the answer may be important to you, if space on the board is a consideration--you can't fit a 24 pin socket in the space where a 14-pin socket can go.

We also want to be mindful of waste in our design, especially for permanent setups. We would like to have every gate actively contributing to our circuit rather than having idle gates here and there. Remember that four idle gates may constitute an extra chip.

Along this line of minimizing waste, the point I'm driving at is this: If you need a NAND gate, and find that you only have an extra AND plus an inverter left idle, you have your NAND gate already on the board by combining these two logic elements. (Take the output of your AND gate and run it through a spare inverter.) In this way, you need not add an extra chip for just one NAND, given that gates come several to a package. If all you have is the AND gate and no spare inverters, consider using a transistor in the common-emitter configuration as an inverter.


Let's suppose you need a 4- input NOR gate, and you only have 2-input NOR gates available on the board.

Trial Solution

You might be tempted to wire the output of gates 1 and 2 together; however, as will be discussed later, this is very often unadvisable. "How about using gates 1 and 2 for the input gates and feeding their outputs into the inputs of gate 3 -- that should get it." Don't speak too soon. Let's analyze it.

Our final configuration of gates should at least perform an OR function, that is, the output state should change whenever any input is raised from 0 to a logic 1. Turning on either input of gate 1 would force its output low; similarly, turning on either input of gate 2 would force its output low. However, moving ahead to gate 3, bringing only one input of gate 3 low, causes no change of state of gate 3--both inputs of gate 3 must go low in order to change the state of its output. Our system has gate 3 changing state ONLY when gate 1 AND gate 2 have an input high.

In addition, there are too many inverters in the chain. When the 4 inputs are low, the outputs of gates 1 and 2 will both be high; in standby (all inputs of the system at 0), output 3 will also be low (remember that gate 3 is a NOR gate).

We have connected up a curious combination of logic which does us no good in our application. While such an interesting logic combination may be quite useful in some applications, it isn't what we had in mind.

Final Solution

To get the result we want, gate 3 must be of the AND logic type. Since the outputs of 1, and 2 are high at standby, they can together cause the output of the AND gate to be high. If any or all of four inputs go high, the output of an input gate will go low causing the output of the AND gate to go low.

Actually, with this discussion, we are getting into the area of "negative logic". The OFF condition of gates 1 and 2 (both NOR gates) produces high outputs; these high outputs hold gate 3 ON (as viewed in positive logic). In a way, we are regarding this ON state of gate 3 as if it were the OFF state. We are looking at gate 3 in terms of negative logic. If you wish to pursue this idea further, the "TTL cookbook" by Don Lancaster discusses it in more detail under "DeMorgan's Theorem", which indicates how a gate in positive logic is regarded when you are thinking in negative logic.

I led you down a garden path in solving that last problem, so you could see, in analyzing a circuit, how easy it is to overlook or to misinterpret a logic operation (especially where inversion occurs). The moral is, "work carefully."

[DeMorgan's Theorem]

[Hang on to your frontal lobes, the next two statements constitute DeMorgan's theorem as your editor barely understood it in college.]


[In our 4-input NOR gate example, consider the third gate (AND) of our final solution. Statement 2 of DeMorgan's theorem says that we can use a NOR gate for number 3 if we "negate" its input signals. As stated, NOT (A OR B) is the function of a NOR gate (A NOR B). Statement 2 of the theorem further goes on to say that this A NOR B is equivalent to NOT A AND NOT B. Well now, A and B, the outputs of the two input gates, can be run through inverters and then fed into a NOR gate like we tried to do in the first place. Furthermore, since the input gates (being NOR gates) already have inverters built into them, we could change these NOR gates to OR gates and scratch the inverters in the input lines of gate 3.]

[Final Final Solutions?

  1. If NOR gates are all we have available, two 2-input units are chosen to get 4 inputs in all. Their outputs each go through an inverter to the final NOR gate. (Note that you can use NOR gates or NAND gates as inverters if you tie their little inputs together.)
  2. Two 2-input OR gates are chosen to get 4 inputs in all. The outputs of these OR gates go directly to the inputs of the final NOR gate.]

[The cookbook series treats DeMorgan?s theorem a little differently. It presents the aforementioned concept of "negative logic", and lists a set of equivalents. "A positive logic NAND gate is the same as a negative NOR gate." "A positive logic AND gate is the same as a negative logic OR gate." By "negative logic", I reckon the inputs and outputs should be negated. As the cookbook states, "you can easily prove this yourself by going back to the truth table and substituting 0's for 1's, and vice versa, to see what happens."]

[What's that you say? "Get that academic windbag out of here!"]

The gates in a package are independent from each other, so that the tasks they perform do not have to be related. As you design a project, keep track of what gates you have on the board, what they do, and which gates you have idle. If the need arises for a NAND gate on one section of the board, and a chip somewhere else in the project has an idle gate or combination of gates that can serve this purpose, it is within the realm of good practice to utilize these unrelated idle gates.

There will be cases where the advantages you gain by including an extra chip are such that you are willing to do so and render idle the sections you don't need. My point is, this choice should be made as a design consideration and not as a matter of happenstance.

In general, do not short-circuit the output of a chip unless it is designed to permit short-circuiting. Going beyond the obvious example of connecting the output to ground with a piece of wire, let us again consider making a 4-input NOR gate out of 2-input NOR gates. You may be tempted to connect the outputs of gates 1 and 2 together. If either input of either gate goes high, the appropriate output will be low. Hence the common connection of outputs will be low. In this way, however, you have short-circuited the output of the gate whose inputs are NOT high. By doing this, you risk exceeding the power dissipation of one of the outputs involved. The situation in which 2 outputs are tied together--where one could be high while the other is low--is to be avoided.

There are "open-collector" gates which can help us in the problem of one-output shorting another. As the name implies, these outputs have no connection committing their collectors (outputs) to either logic level. You can provide one external pull-up resistor for many such outputs. Since there is only one resistor, you do not have to worry about one output unduly dissipating power.

There are chips which are said to be of the "tri-state logic" type. This system allows, in addition to the logic high and low, a high impedance or open circuit state where the output is committed to neither. (Don't confuse this with base 3 arithmetic; it is still binary.) The high-impedance state is usually controlled by one control line which affects all the gates in the chip.

Tri-state devices are used when you have several chips which could output onto a common partyline bus to drive other equipment. You would arrange your control logic so that only one set of outputs can be sending at a time.

Remember, time waits for nothing, not even IC's. We often blithely make statements like, "The input and output of an inverter are always in a NOT relationship." With experience, you are going to learn that you must use such words as "always" and "simultaneous" rather carefully. While as a practical matter, B = NOT A holds true for the inverter, there is still an extremely small--but nevertheless real--period of time during which A and B can actually be equal.

Suppose the input of an inverter is high as we begin our examination; the output will be low. The role of this output is to respond to, and not initiate, a change of state. Since the output does not know when the input is going to change, we must agree that the input will have to change before the output can change. Once you admit that word "before", you admit that a time interval (though small indeed) exists. Thus, when we switch the input to the OFF state, a small period of time (a few nanoseconds) occurs during which IN is OFF and OUT is also OFF.

"Why worry about this very small period of time? Isn't that the manufacturer's problem?" If you have several gates operating in one system, and you are driving or "clocking" this system in the range of RF, the delays of all these gates add up. This delay time can, under certain conditions, flaw your project's operation. Manufacturers publish "propagation times" in their data sheets. While you can often overlook propagation delay times in DC and low frequency projects, at RF you might be wise to take note of these statistics. Remember, those complex digital chips you buy are, after all, a whole mess of gates connected to perform the desired operation. Counters, registers, etc. are built from flip flops; flip-flops are built from gates, and gates are often based on inverters.

[In general, logic of the TTL type is "faster" than CMOS.]

There are "clocked-logic" chips which synchronize the switching of all their gates in order to cut down their propagation times. Basically, these chips arrange for one clock line to serve as a common "enable" signal for strategic AND gates in the device. The inputs, internal and external, are first set up to their needed states to predetermine the next action of the chips. Then, the clock pulse meets the remaining conditions of the strategic AND gates, and the chips operate as one entity.

Chips such as "tri-state logic" and "clocked-logic" are somewhat harder to find than garden-variety logic circuits-I doubt that they would be your first choice, especially if you are a beginner. But as you advance in the study of logic circuits, remember that these more exotic chips are available. In the meantime, you will be surprised how many interesting circuits you can build with only a few of the simpler chips.

Let's meet a few chips

(Note--TTL logic operates on 5 volts plus or minus 5 %. CMOS, on the other hand is much less critical, and many of these chips can be operated from supply voltages ranging from 3 to 15 volts.)

Hex-inverters and buffers--the input and output of an inverter is always in a NOT relationship, i.e. B = NOT A

[In print, "not" is indicated by a horizontal line (termed "bar") over the symbol to be negated, that is, B = A superscribed with a bar. In Nemeth code, a bar is represented by a Braille "wh" sign following the symbol. Proper Nemeth code requires that this "wh" bar sign be preceded by a "gh" sign to take it above the line, and followed by an "er" sign to bring it down to the base line. Bill Gerrey's simplified Nemeth Code dispenses with these raising and lowering symbols, so that the negated input can be written "Awh".]

The TTL 7404 contains six independent inverters.

7404 Hex-Inverter:

  • Pin 7--Ground
  • Pin 14--VCC
  • Pin 1--IN 1
  • Pin 2--0UT 1
  • Pin 3--IN 2
  • Pin 4--OUT 2
  • Pin 5--IN 3
  • Pin 6--0UT 3
  • Pin 8--0UT 4
  • Pin 9--IN 4
  • Pin 10--OUT 5
  • Pin 11--IN 5
  • Pin 12--0UT 6
  • Pin 13--IN 6

The 4049 CMOS hex-inverter/buffer can be used for logic inversion. In addition, it has the advantage of allowing its inputs to go above the supply voltage, making it ideal for working as a buffer between CMOS and TTL logic.

The 4050 CMOS buffer is non-inverting. It is strictly a buffer; it performs no logic function, i.e. OUT = IN

Let me give you a hint as an experimenter: If you need a buffer in an experimental project, buy the inverting buffer. You will often have one or two sections of this device left idle. If you need an inverter somewhere, you'll have it. Had you bought the straight (non-inverting) buffer, your spare sections could do no logic operations for you.

4049 CMOS Inverter/Buffer and 4050 Non-Inverting Buffer:

  • Pin l--Plus Supply
  • Pin 8--Ground
  • Pin 2--OUT 1
  • Pin 3--IN 1
  • Pin 4--OUT 2
  • Pin 5--IN 2
  • Pin 6--OUT 3
  • Pin 7--IN 3
  • Pin 9--IN 4
  • Pin 10--OUT 4
  • Pin 11--IN 5
  • Pin 12--OUT 5
  • Pin 13--NC (no connection)
  • Pin 14--IN 6
  • Pin 15--OUT 6.
  • Pin 16--NC (no connection)

2-Input Gates--The CMOS 4001 is a quad 2input NOR gate, and the 4011 is a CMOS quad 2-input NAND gate. The same pin-out holds for both.

(Note that I have juggled the pin numbers around to facilitate understanding of the chip lay-out. The inputs of the gates go to pin numbers nearest the corners of the chip, and output connections are near the middle of either side. Note also that the + V supply terminal is marked VDD instead of VCC. This is the accepted notation, since the power is not supplying collectors of transistors, but drains of FET's.

4001 NOR, 4011 NAND:

  • Pin 7-----Ground
  • Pin 14----VDD
  • Pin 1,2---IN 1
  • Pin 3-----OUT 1
  • Pin 5,6---IN 2
  • Pin 4-----OUT 2
  • Pin 8,9---IN 3
  • Pin 10----OUT 3
  • Pin 12,13-IN 4
  • Pin 11----OUT 4

I might insert here for those who have never seen printed schematic diagrams or the printing on chip packages, that labels such as IN 1 and OUT 1 were added by this writer for presentation in non-diagramatic form. On the packages of chips, there is often a diagram showing pin numbers around the perimeter of a rectangle; schematic symbols of the gates inside the rectangle have their inputs and outputs running out to the appropriate pin numbers. If you go to the parts store and ask the salesman to read you the pin diagram, he may tell you that all he sees are pin numbers and little lines. I have learned this since I have begun reading such material with an Optacon and I would like to share this knowledge with you.

Once again, we can use one pin diagram for two chips, 7400 and 7408 TTL gates. The inputs and outputs are the same, but remember that their logic is different.

To broaden your experience with different notations, I'll use a type of labeling that Radio Shack uses in their data manuals.

7400 NAND, 7408 AND:

  • Pin 7--Ground
  • Pin 14--VCC
  • Pin 1--A 1
  • Pin 2--B 1
  • Pin 3--Y 1
  • Pin 4--A 2
  • Pin 5--B 2
  • Pin 6--Y 2
  • Pin 8--Y 3
  • Pin 9--A 3
  • Pin 10--B 3
  • Pin 11--Y 4
  • Pin 12--A 4
  • Pin 13--B 4

7402 NOR gate:

  • Pin 7--Ground
  • Pin 14--VCC
  • Pin 1--Y 1
  • Pin 2--A 1
  • Pin 3--B 1
  • Pin 4--Y 2
  • Pin 5--A 2
  • Pin 6--B 2
  • Pin 8--B 3
  • Pin 9--A 3
  • Pin 10--Y 3
  • Pin 11--B 4
  • Pin 12--A 4
  • Pin 13--Y 4

The chips and ideas presented here should help acquaint you with the basic concepts of gates and logic circuits. To coin a pun, your understanding of digital logic and of counters and registers must begin by walking through all kinds of gates. But take heart, you can take it one gate at a time.


In order to promote understanding of terms such as TTL and CMOS, the following equivalent circuits are presented.

For many logic types, there is one specific gate which is intrinsically easiest to make. For example, many TTL devices are based on NAND gates, and electronic trickery and De Morgan's theorem must be used by the manufacturer to make NOR and AND gates. (In engineering school, TTL design projects were down-graded if AND and NOR gates were used extensively. This was done because of their higher cost and to promote use of De Morgan's theorem.)

RTL (Resistor-Transistor Logic)

Although very obsolete, this circuit can serve as an example, since RTL is the simplest of gates. A multi-input NOR gate can be made with one transistor and several input resistors. The emitter of an NPN transistor is grounded. The collector, which becomes the output of the gate, goes through a pull-up resistor to VCC. The base of this transistor goes through a resistor to each one of the input terminals. If any input goes high, the base gets forward biased (turning on the transistor), and the output drops to a logic low. (There is usually a resistor from base to ground to assure that the transistor is turned off when inputs are left open.)

DTL (Diode-Transistor Logic)

You may come across this type of logic occasionally. It is sufficient to say that the base bias of the common-emitter transistor is controlled through a network of diodes instead of the resistors found in RTL.

TTL (Transistor-Transistor Logic)

This system uses a transistor on each input to control the final common-emitter output stage. The output transistor has its emitter grounded. Its collector, the output of the gate, goes through a pull-up resistor to VCC. Collectors of several input transistors all go directly to the base of the output stage. The bases of these input transistors all go through a common resistor to VCC. The emitters are the inputs.

This basic TTL circuit performs a NAND function. Grounding the emitter of any input transistor turns it on causing its collector to turn off the output stage.

On the other hand, if all the inputs are either high or left open, the base collector junctions of the input transistors become forward-biased diodes which allows their common base resistor to turn on the output stage.

The inputs of TTL devices are not simply "voltage controlled". About 1.6 mA of input current has to be drawn from an input emitter to saturate an input transistor. These essential input conditions can best be met by either "contact closure" (shorting an input to ground through contacts of a switch) or an "active pull-down" circuit (pulling an input down with the collector of an NPN transistor). In addition, the gate's output is best able to pull down on its load, and it is able to pull down a current of 16 mA. Note that one output is able to pull down ten inputs; the "fan-out" for TTL logic is ten.

The above input and output conditions must be taken into account when interfacing TTL with other electronic components.

Although TTL is noted for its high speed, even faster logic can be made by connecting Schottky diodes across various transistor junctions to keep these element from going into hard saturation. Schottky TTL devices have an S in the middle of their chip number, like 74S123.

TTL is noted for its very high current drain; all those gates in a project add up to something rather magnitudinous. Special low-powered chips are available whose internal resistors (base and collector resistors) are of larger value. Input and output currents are consequently reduced to about 1/5 of regular TTL specifications. Chips of this type have an L. in their designation number. A Schottky low power chip would have a number like 74LS123.

CMOS (Complimentary Metal-Oxide Semiconductor) logic

As you might expect, these devices are made up of complimentary sets of P-channel and N channel MOSFET's. The individual FET's operate in the "enhancement" mode, i.e. they are turned on with a forward bias on their gates. (Note that in the discussion of equivalent MOSFET circuits, we cannot avoid using the term "gate", which is the controlling element of FET's. We must be careful to distinguish gates of FET's from logic gates.) Using complimentary elements makes it easy to construct both NOR and NAND gates.


Two N-channel FET's (01 and 02) are connected in parallel; their sources are grounded and their drains go to the output. Between these drains and VDD (the positive supply voltage) are two series-connected P-channel FET's (Q3 and Q4); the source of Q4 goes to VDD, its drain goes to the source of Q3, and the drain of Q3 goes to the two N-channel drains and to the output. The gates of Q1 and Q4 go to the A input. The gates of Q2 and Q3 go to the B input.

Each input controls one N-channel FET and one P-channel FET. When an input is low, its N-channel FET is open and its P-channel PET is closed. When an input is high, its N-channel FET is closed and its P-channel FET is open. When both inputs are at logic 0, the series-connected FET's between the output and VDD are closed to pull the output up to a logic 1, and the parallel-connected FET's are both open so as to disengage this output from ground. Raising either input to a logic 1 shorts the output to ground through one of the paralleled FET's, and one of the series-connected FET's obligingly opens.


This time, parallel-connected p-channel FET's (Q3 and Q4) go from the output up to VDD, while series-connected N-channel FET's (Q1 and Q2) go from the output to ground. The source of Q1 is grounded, the drain of Q1 goes to the source of Q2, and the drain of Q2 goes to the drains of Q3 and Q4 and to the output. The sources of Q3 and Q4 both go to VDD. The gates of Q1 and Q4 go to input A, and the gates of Q2 and Q3 go to input B. Any low input will open a series-connected FET between the output and ground, and the output will be shorted to VDD through a parallel connected p-channel FET. If both A and B are high, the paralleled PET's will be open and both series-connected FET's will short the output to ground.

The output current available from CMOS logic is comparatively low, about 0.25 mA. As you can see, emitter-follower stages or other buffers (such as the 4049 and 4050) are needed to control anything with these devices. Because of their insulated gates, however, the fan out for these gates is large.


The key ingredient of a flip-flop is that two gates are cross-connected. A TTL flip-flop has two NAND gates connected with the B-input of gate 1 going to the output of gate 2, and the B- input of gate 2 going to the output of gate 1. With the free inputs tied high this configuration is "bi-stable", i.e., the flip-flop is content to sit in either of two states--the output of 1 high and the output of 2 low, or vice versa. The states of the outputs can be "toggled" back and forth by grounding the free input of the gate, whose B-input is initially high (this gate's output will be low to start with). The output of this gate will jump to a logic 1, and the output of its mate will go to 0.

Traditionally, the output of gate 1 is labeled Q, and the output of gate 2 is labeled NOT Q. (As mentioned in "Gabbing about Gates", NOT Q is often written as Q superscribed with a line and is read "Q bar")

The two free inputs are often labeled SET and RESET (S and R), and the above flip-flop circuit is termed an R-S flip flop. (Actually, the CMOS cook book informs me that flip-flops using NOR gates have truly RS inputs, and that those using NAND gates technically have NOT R-NOT S inputs.)

In the case of our TTL flip-flop made of NAND gates, lowering both R and S inputs causes an argument between the two gates, and this is called the "disallowed state". If we had a flip-flop made of NOR gates, the disallowed state would occur when both free inputs are high.

In our TTL example, the gates are perfectly comfortable resting in either state while both inputs are high. Bringing the A input of gate 2 (RESET) down to 0 assures that the flip-flop is "cleared", i.e., Q becomes 0 and NOT Q goes to 1. If the flip-flop was in this position to begin with, nothing will change when RESET is brought to 0. Bringing the A-input of gate 1 (SET) to 0 will assure that the flip-flop goes to the "preset" state, Q = 1 and NOT Q = 0. Further triggering of this SET terminal will cause no change, so long as Q = 1 and NOT Q = 0.

The terms "RESET" and "CLEAR" are synonymous, as are the terms "SET" and "PRESET". This was done in a deliberate attempt to confuse beginners like us.

Briefly, various accessory circuits (master-slave connections of flip-flops) are incorporated into IC chips to control the basic RS flip-flop at the output. The chips you are likely to use may have the following terminals:

  1. CLEAR or RESET--This terminal assures the establishment of Q == 0 and Q bar = 1.
  2. PRESET or SET--This terminal assures the condition that Q == 1 and Q bar == a
  3. TRIGGER or CLOCK input--In sophisticated flip-flop set-ups, this one terminal can be used to toggle the flip-flop back and forth. It is designed to "edge-trigger", i.e., toggle the flip-flop during a transition of its clock signal. Depending on the chip, triggering can be accomplished on either the leading edge or the trailing edge of the clock pulse.
  4. J and K inputs--(These are not to be confused with PRESET and CLEAR, which override the operation of the clock terminal.) The J and K terminals can be used to guide subsequent toggling of the flip-flop. J and K set the device up for one more flip or one more flop, respectively. Bringing both J and K low permits the flip-flop to rest in either position ignoring activity in the trigger terminal. If J is high and K is low, the next clock pulse will cause the device to flip and stay flipped (Q = 1 and Q bar = 0); if it was already in this state, J signals it to stay there. On the other hand, if K is brought high and J is low, the next clock pulse will cause the device to flop and stay flopped (Q = 0 and Q bar = 1); if it was already in this state, K signals it to stay there. Finally, if both J and K are high, clock pulses will continually trigger (alternately flipping and flopping) the device.
  5. D (DATA) input--The J and K functions are sometimes combined into one terminal (DATA input). The Q output will follow on a subsequent clock pulse wherever D has been set. In other words, if D is brought high, the next clock pulse will bring Q high (or leave it there, if Q already was high). If D is brought low, the next clock pulse brings Q low (or leaves it low, as the case may be). To make a D flip-flop toggle continuously, D can be tied to the NOT Q, terminal, thereby continually setting the device up for a new change of state.


The timer circuit of the Smith-Kettlewell battery charger (winter, 1981) contains a string of 16 flip-flops (dividers) in cascade. (Eight flip-flops are contained in each XR2242 chip.) A "clock" oscillator feeds the trigger of the first, the Q of the first feeds the trigger of the second, the Q of the second feeds the trigger of the third, and so on down the line. Each flip-flop triggers on the trailing edge of its triggering signal. Two descending pulses of the clock flip and flop the first, two flops of the first, flip and flop the second (during which 4 clock pulses have occurred), 2 flops of the second flip and flop the third (during which 8 clock pulses have occurred). This goes on until the sixteenth "divider" flips, at which point the Q of this flip-flop "clears" everything and stops the clock. (Note that if these circuits were flipping on the leading edge of their triggering signal, they would all have flipped on the first clock pulse. We could have used this type, if we were to couple them together via Q bar.)

Note that each flip-flop divides the frequency of its triggering signal by 2. To run a flip-flop through a complete cycle, it must be flipped and flopped, i.e., it must be toggled with 2 cycles of its triggering signal.


OK, we can divide the frequency of a clock by 2,4,8,16, etc., but where I went to school, we were taught to think in terms of 10's. How can we divide by 10?


Let us set up a series of 4 flip-flops, creating a system that divides by 16. Just as in the timer of the battery charger, the output of each flip-flop goes to the trigger terminal of its successor, and a clock signal will be fed to the trigger of the first. If they are JK elements, both J and K of each flip-flop should be tied high. If D flip-flops are used, tie each D terminal to its own Q bar.

While taking a long shower and thinking it over, we see that the 10th clock-pulse will put the outputs of the first and third low and the outputs of the second and fourth high. We can connect the second and fourth outputs to the inputs of an AND gate, and use the output of this AND gate to "clear" the flip-flops back to zero. This assumes a 1 is needed for "clear". Clock pulses 0 through 9,have our counter dividing as normal--then, all of a sudden, the clear terminal gets pulled up to abort the mission.

Drat, we only have NOR gates available. Connect a NOR gate's inputs to Q bar of the second and fourth flip flops, and connect the output of the NOR gate to the "clear" terminals as before.

A cascade of flip-flops can be used to "count the clock pulses (in the binary number system). Suppose we connect a push-button switch (in place of the clock signal) to a string of flip-flops. To do this, let's run the trigger terminal of the first flip-flop through a push-button switch to ground, and we shall tie the trigger input high through a pull-up resistor of perhaps 10 KOhms. We have now set up a counter which can be operated manually.

Every time we push the switch, the trigger terminal will go through a transition from high to low; releasing the switch allows the pull-up resistor to bring the trigger terminal through a low-to-high transition. One of these transitions will trigger the counter, depending on the chips used. Let us choose circuits which flip on the negative transition of the triggering signal, otherwise the counter will actually count backwards.

Just for fun, let's give our little counter a read-out system. The simplest and cheapest would be to use light emitting diodes (LED's), one for each flip-flop. (Note that if we were to use CMOS flip-flops, we would have some interfacing to do, because of their inability to supply enough current to light the LED's. Therefore, let's use TTL devices and take advantage of their high-current capability.) TTL devices pull down on their load, so we must run each LED between its flip-flop output and VCC. We'll have to use Q, bar for this trick, otherwise the lamps would come on for an output of 0. Connect the anodes of all four diodes to VCC and run each cathode through 270 Ohms to the output of its flip-flop.

We now have a counter which indicates the number of button pushes in terms of 1?s and 0's. You ask, "what good is a counter that registers a number of events in terms of Q1 = 1 and Q2 = 0 etc.? " The answer to this question lies in the next article ("Counting in Base 2").

One-shots?Hey! How come the performance of our counter is erratic? Pushing the button sometimes causes the counter to jump ahead 2, 3,or 4 counts. What's wrong?

Logic circuits are so fast that they can count bouncing of the contacts in a switch. For this and other applications, what we need is a little one-shot, which cannot be purchased by the liter.

One-shot circuits have cross-connected gates with RC coupling, so as to be "monostable". Operating on a different principle is the NE555, which can also be wired as a one-shot. In any case, one-shots can be flipped, but the charge state of a capacitor determines that they only stay flipped for a specified length of time, after which they revert back to their original state. One-shots trip once--when they flip, they flip. Thus, one-shots are just the thing for cleaning up "muddy" input signals and for eliminating the contact bounce of switches.

To clear up our counter's problem, we will trip a one-shot with the switch (using the same switch circuit on its input), and feed the output of the one shot directly into the trigger terminal of the first flip-flop.

General comments

Both TTL and CMOS chips (from the 7400 series and 4000 series, respectively), are listed here. Note the differences in pin connections between the two types.

In a noble attempt to simplify matters, National Semiconductor has brought out a new series of CMOS chips, whose pin connections are directly patterned after the good ol' 7400 series. National's digital logic chip numbers begin with the prefix MM, and the letter C in the middle of the number denotes CMOS; a CMOS 7408 is an MM74C08.

TTL devices are as old as the hills and your editor. For your information, formal numbers of Texas Instruments begin with the prefix SN, e.g., SN7408. The 4000 series (CMOS devices) are the brain child of RCA, and formal numbers have the prefix CD, e.g., CD4001. Motorola CMOS numbers begin with MC1, e.g., MC14001

JK Flip-Flops

7473 (Triggers on negative transition of the clock pulse):

  • Pin 4--VCC
  • Pin 11--Ground
  • Pin 1--CK1 (clock)
  • Pin 2--CLR1 (low for clear)
  • Pin 3--K1
  • Pin 12--Q1
  • Pin 13--Q bar 1
  • Pin 14--J1
  • Pin 5--CK2 (clock)
  • Pin 6--CLR 2 (clear)
  • Pin 7--J2
  • Pin 8--Q bar 2
  • Pin 9--Q2
  • Pin 10--K2

4027 (Triggers on the positive transition of the clock pulse):

  • Pin 8--VSS (ground)
  • Pin 16--VDD
  • Pin 9--SET1 (high for set)
  • Pin 10--J1
  • Pin 11--K1
  • Pin 12--RESET1 (high for reset)
  • Pin 13--CK1 (clock)
  • Pin 14--Q bar 1
  • Pin 15--Q1
  • Pin 1--Q2
  • Pin 2--Q bar 2
  • Pin 3--CK2 (clock)
  • Pin 4--RESET2
  • Pin 5--K2
  • Pin 6--J2
  • Pin 7--SET2

D Flip-Flops

7474 (Positive edge triggered):

  • Pin 7-Ground
  • Pin 14--VCC
  • Pin 1--CLR1 (low for clear)
  • Pin 2--D1
  • Pin 3--CK1
  • Pin 4--PR1 (low for preset)
  • Pin 5--Q1
  • Pin 6--Q bar 1
  • Pin 13--CLR2
  • Pin 12--D2
  • Pin 11--CK2
  • Pin 10--PR2(preset)
  • Pin 9--Q2
  • Pin 8--Q bar 2

4013 (Positive edge triggered):

  • Pin 7--VSS (Ground)
  • Pin 14--VDD
  • Pin 1--Q1
  • Pin 2--Q bar 1
  • Pin 3--CK1
  • Pin 4--RESET1 (high for reset)
  • Pin 5--D1
  • Pin 6--SET1 (high for set)
  • Pin 13--Q2
  • Pin 12--Q bar 2
  • Pin 11--CK2
  • Pin 10--RESET2
  • Pin 9--D2
  • Pin 8--SET2



(For trailing edge triggering tie B to VCC, for leading edge triggering tie A to ground. Of course, operate the free trigger input):

  • Pin 8--Ground
  • Pin 16--VCC
  • Pin 1--1A (low level)
  • Pin 2--1B (high level)
  • Pin 3?CLR1 (low for clear)
  • Pin 4--Q bar 1
  • Pin 13--Q1
  • Pin 14--Cext1 (C external)
  • Pin 15--Rext1 and Cext1
  • Pin 5--Q2
  • Pin 6--Cext2
  • Pin 7--Rext2 and Cext2
  • Pin 9--2A
  • Pin 10--2B
  • Pin 11--CLR2 (low for clear)
  • Pin 12--Q bar 2

(R = from 5 to 50 kOhms and goes between Rext and VCC. Cext goes between pins 14 and 15, and 6 and 7. In general, t (nanoseconds) = .28 RC (1+.7/R), where R is in kOhms and C is in picofarads.

4098 or 4528

(for trailing edge triggering, tie plus TR to VSS, for leading edge triggering, tie minus TR to VDD. Of course, operate the free trigger input):

  • Pin 8--VSS
  • Pin 16--VDD
  • Pin 1--CX1 (C external)
  • Pin 2--RX/CX1 (R and C external)
  • Pin 3?RESET1 (high for reset)
  • Pin 4--plus TR1
  • Pin 5--minus TR1
  • Pin 6-Q1
  • Pin 7--Q bar 1
  • Pin 15--CX2
  • Pin 14--RX/CX2
  • Pin 13--RESET2
  • Pin 12--plus TR2
  • Pin 11-minus TR2
  • Pin 10--Q2
  • Pin 9--Q bar

(Minimum RX is 5 kOhms, maximum CX is 100 uF, minimum CX = .01 uF. T = .5 * RX * CX)


(Negative edge triggering):

  • Pin 1--Ground
  • Pin 8--VCC
  • Pin 4--Enable (Grounding sends output low and locks it there)
  • Pin 5--Control Voltage (Not used for one-shot)
  • Pin 6--Threshold
  • Pin 7--Discharge
  • Pin 2--Trigger
  • Pin 3--Output

(Pins 6 and 7 are tied together and go through R to VCC, and through C to ground. T = 1.1*R*C. Unlike other one-shot circuits, holding the trigger terminal down longer than time t holds the output down also, i.e., the trigger pulse must be shorter than t in order for this formula to hold.)


Once you get used to doing it, it is very easy to convert binary numbers to something we understand. Each digit is either one or nothing--no in betweens are permitted. The information contained in each digit is rudimentary-you have one or you do NOT have one. The fact that only two states are possible (binary) has led people in the digital world to invent a simple term for the amount of information contained in each digit, they call it a "bit" (short for Binary digIT).

The placement of a digit in a number indicates its real value (3 in 34 means 30, but 3 in 377 means 300).Thus the placement in the group of digits defines its "digit value". The total value of a group of digits in any number system is the sum of the individual digit values. Thus, 30 plus 4 = 34 and 300 plus 70 plus 7 = 377.

As an example of how a binary number accumulates as counting proceeds, let us consider the operation of a four flip-flop counter, like that discussed in "Flip-Flops". This is known as a four-bit counter. A cascade of four flip-flops is set up to count the closures of a push-button switch. The switch trips a one-shot which feeds into the trigger terminal of the first flip-flop, the output of the first flip-flop triggers the second, the output of the second triggers the third, and the output of the third triggers the fourth. The "CLEAR" terminals of all four flip flops are connected in such a way that the counter can operate uninterruptedly, after initially setting all outputs to zero. Finally, indicator lamps are connected to the flip-flop outputs to indicate the logic state of each bit.

The "bit" closest to our push-button changes every time its flip-flop is triggered: it is the "least significant figure". The last flip-flop down the line changes only after many clock pulses (operations of the push-button), so this bit must be quite valuable in comparison: this bit is the "most significant figure". The first flip-flop changes at every trigger pulse; it is worth "one". The second flip-flop changes every two clock pulses: it is worth "two". After four clock pulses, the third flip-flop comes on to say "four". Finally, the last one comes on to tell us "eight".

The four bits are worth one, two, four, and eight. To be consistent with the way we normally value digits, let's put the least significant digit at the right, i.e., orient our counter so that the push-button system is triggering the right-hand flip-flop. We can now read the output of the counter as: 1111=8+4+2+1=15. To aid in interpreting a binary number, we can attach labels above these lamps to indicate their "value" in the decimal system.

We can read our lamps as binary numbers, namely 0001,0010,0011,0100, etc. Taking their "values" into account, we can state the following examples: Of course, 0000 means "0", and 0001 means "1". Now, 0010 means "2" (the lamp in the 2's place is on and nothing else); 0011 means "3" (both "two" and "one" are on) 0100 means "4" (the "four" lamp is on). In the same way 0101 means "5", 0110 means "6", and 0111 is "7" (because 4+2+1=7). The highest number possible for this four-bit system is 1111, which is 8+4+2+1=15.


The zip code of the American Foundation for the Blind is 10011. How does Bill Gerrey remember this fact?


Consider 10011 as a five- bit binary number with "values" of 16,8,4,2, and 1. 10011 is 16+ NOT8 +NOT4+2+1,=16+2+1=19. So, all he has to remember are two digits. Clever, non?


We want to invent a digital writing system to avoid all those squiggly lines found in normal calligraphy. In other words, instead of lines we will make symbols using patterns of dots. We decide that we could say just about everything we want to say with 63 characters. How many dots do we need in combination to form this many characters?


For a given number of dots, we must find out how many combinations are possible. We reason that if each dot were represented by a digit in a binary number, counting from 0 on up to a complete string of 1's will exhaust all possible combinations for a given number of bits. Now, how large does a binary number have to be to make it up to 63? In other words, how many bits do we need?

Suppose we try a 5-bit number like AFB's zip code. Make all five digits 1; we have 11111, i.e. 16+8+4+2+1=31.

Now let's try six bits-- remember, each additional bit is worth twice as much as the one to it's right. 111111 is 32+16+8+4+2+1=63. Voila!

As you may already have guessed, someone beat us to it with this invention, and he finished working it out at the age of fifteen years. His name was Louis Braille.


You are vacationing on the planet Binarus. You find that their monetary system is binary and their currency is marked like 00010000 or 00000100. It has been arbitrarily decided that one of your dollars is worth one of their "billars". You step into a gambling casino and hand the cashier $20. He makes a face, converts 20 into a binary number and hands you your change. What value chips does he give you?


Each chip he has is related by a factor of two to the next larger or the next smaller in size. He does have a denomination of 1 billar (00000001). The next size up is 10 billars ($2). The size above that is 100 billars ($4). In billars he finally gives you chips of 00010000 and 00000100 billars, which amounts to 16+4=$20.

While lounging, you strike up a friendship with a little green couple, and attempt to explain your very strange money to them. The little green lady and her husband pullout all their money and place it on the table for comparison. She appears to have much more money than he has. (She has control of the purse strings as it should be done in an advanced civilization).

He has 10 billars, and you explain that this is worth two of your dollars. She on the other hand has 00100000 billars, which works out to be $32.

Stricken with inspiration, you pullout $1000 in traveler's checks and convert this amount into binary: 512 + 256 + 128 + 6'1 +32 + 8= 1111101000.

Waving your hand and shrieking, "I'm rich! I'm rich!" brings on a deluge of little green realtors tripping over each other to sell you some boperty. Your elation is short-lived, since all you can get for 1111101000 billars is $1000 worth of wasteland on the dark side of the planet.

Addition and Subtraction

This information is "nice-to-know" (NTK), rather than being in the category of "have-to-know" (HTK). As we discuss microprocessors in future issues, this will give us insight as to what operations the computer chip is actually performing.


Adding 0's (0 + 0) and adding 1?s to 0's (1 + 0) is trivial. However, what happens when we have 1 + 1 ? You can't get 2, because there is no such thing as 2. 1 + 1=0 and carry 1= 10.


What is 10011 + 00111?


Adding the columns from right to left, we get: 1.) 1 + 1=0 carry 1. 2.) 1 + 1 is 0 carry another 1, plus the "carry bit" from step 1, i.e., 1 + 1=0+1=1 carry 1. 3.) 0+1=1, plus the carry equals 0,carry 1. 4.) 0+0=0 plus the carry equals 1. 5.) Finally, 1+0=1. The answer is 11010. We can check this by converting these binary numbers into decimal numbers and doing the problem in base 10.

  1. 10011 is 16+2+1=19 (AFB zip code).
  2. 00111 is 4+2+1=7.
  3. 19+7=26.
  4. 16+8+2=26 and that is 11010.


(The following procedure seems difficult, but note that computers do not subtract numbers, they can only add.)

It is possible to pick a complimentary subtrahend (bottom number) so as to permit getting the answer by adding this compliment to the minuend (top number). First, the subtrahend is converted to its "2's compliment" (compliment in the binary system). Second, this compliment number is added (not subtracted) to the minuend, and the carry bit which spills over to the next column is thrown away.

The 2's compliment of a binary number is easily gotten, just change all the 0?s to 1?s and vice versa, then add 1 to the least significant digit.

For example, the 2's compliment of 10011 is 01100 + 1= 01101. Before you derive this compliment, make sure that the subtrahend and the minuend have the same number of digits; if they do not, hang D's on the left end of the shorter number until this condition is achieved. (Note that electrically speaking, changing 0's to 1's and 1's to 0's is the same as inverting all the binary outputs, i.e., it is like hooking up to the "q bar" outputs instead of "q", see "Flip-Flops". )


How about 110011 (6-3)?

  1. 110 is the minuend, we leave it alone for the moment.
  2. We need the 2's compliment of 011, which is 100+1=101.
  3. Adding 110+101 from right to left: 0+1=1; 1+0=1; finally, 1+1=0, and we throwaway the carry bit. The answer is 011.

Let's pull a similar stunt in base 10. In decimal, the problem was 6-3. The lots compliment of 3 is 10-3=7. Adding 6+7 gives us 13; without the carry we are left with an answer of 3.


What is the editor's age minus AFB's zip code, 100010 minus 10011?


First, we must re-write the problem so that the subtrahend has as many digits as the minuend, 100010 - 010011.

The 2's compliment of 010011 is 101100 + 1=101101.

Finally, 100010+101101= 1001111; discarding the carry bit gives us 001111.

Binary Coded Decimal (BCD) System

Technologists in the computer industry have found themselves obliged to tailor the outputs of their machines to our old-fashioned system of decimal arithmetic, otherwise we would not have paid attention to them. The binary-coded-decimal (BCD) system is a way to interface digital electronics with decimal devices.

BCD assigns a 4-bit binary number to each digit of a decimal number. Each decimal digit can range in value from 0 through 9. A 4-bit binary number is sufficient to cover this range of values (a 3-bit binary number can only count from 0 through 7). As has already been shown, a 4-bit binary number can actually count from 0 up through 15, since 8+4+2+1=15. BCD wastes values 1015 of the binary number, 1010-1111, and considers these values to be undefined.


Since each digit has assigned to it a 4-bit binary code, numbers must be written as follows:

19 has 1 in the 10's place, and 9 in the 1's place. The 1 and the 9 are represented by the binary codes 0001 and 1001, respectively. In the same way, 34 is expressed as 0011 0100.


Consider our 4-bit counter made with four flip-flops. This time we will connect a 2-input AND gate so as to "sense" the number ten (1010), and connect this AND gate's output to the "clear" terminals of all four flip flops (assuming a logic "I" on the "clear" terminals resets the devices). The counter will count from 0 through 9 without interruption, but 1010 kicks it back to 0000 again. This is known as a "ring counter", and its sole purpose is to represent one decimal digit in a binary code.

To get the next digit (in the 10's place), we shall use the brief pulse found on the "clear" terminals of the first counter to advance the count of a second ring counter, which is dedicated to the 10's place. These two 4-bit counters give us the 4bit codes to represent two decimal digits. Now that we have these 4-bit binary numbers, what do we do with them? We can dedicate a 4input AND gate to each decimal number.

For example , an AND gate with its inputs on the q bar terminal of the four flip-flops will show us when "0" occurs. We can connect 4-input AND gates to various combinations of q and q bar to "detect" the various decimal numbers. 0011 is 3--an AND gate with its inputs on NOT Q,NOT Q,Q,Q will show us when the conditon 0011 occurs. (Some very early electronic calculators used cascades of ring counters to simulate the spinning wheels found in mechanical units.)

Seven-segment Display System

Seven-segment displays are those found on pocket calculators and other digital instruments. The seven-segment format is of considerable interest to us, since many instrumentation chips (such as voltmeter and frequency counter chips) have outputs designed for driving these displays.

Each numeral is described by seven LED bars. The bars are arranged so as to construct a square figure 8 pattern. In other words, the perimeter of the array uses 6 segments to form a rectangle two bars high and one bar wide, with the seventh segment bisecting this rectangle into two squares, one above the other. Starting from the top and moving clock wise, the bars around the perimeter are denoted a, b, c, d, e, and f, and g is the horizontal bar across the center. Some examples of numerals are: 8 is made by illuminating all seven segments. 0 is made by illuminating a through f. Seven is made of a, b, and c. Depending on the display, 1 can be either b and c or e and f. Numbers 6 and 9 include all except band e, respectively. (Occasionally 6 and 9 leave out a and d as well.) 2,3,4, and 5 are as you might expect.

Meeting New Chips

Nowadays, chips are available with sets of built-in AND gates for converting BCD into other formats. The first chip presented here (7442) has four BCD inputs, and ten outputs for 09, it is known as a BCD-to-Decimal Decoder. The second chip (7446) is used to drive 7-segment displays. The third chip (74C915) converts the seven-segment format back into BCD; this is very important for driving speech-boards from digital instruments with seven-segment displays.


(TTL, BCD-to-decimal decoder):

  • Pin 8--Ground
  • Pin 16--VCC
  • Pin 1--0
  • Pin 2--1
  • Pin 3--2
  • Pin 4--3
  • Pin 5--4
  • Pin 6--5
  • Pin 7--6
  • Pin 9--7
  • Pin 10--8
  • Pin 11--9
  • Pin 15--A (least significant bit)
  • Pin 14--B
  • Pin 13--C
  • Pin 12--D (most significant bit)


(TTL,BCD-to-seven segment decoder):

  • Pin 8-Ground
  • Pin 16--VCC
  • Pin 1--B in
  • Pin 2--C in
  • Pin 6--D in (most significant bit)
  • Pin 7-A in (least significant bit)
  • Pin 9--e out
  • Pin 10--d out
  • Pin 11--c out
  • Pin 12--b out
  • Pin 13--a out
  • Pin 14--g out
  • Pin 15--f out
  • Pin 5--ripple-blanking input (if low, 0 is suppressed)
  • Pin 4--blanking input and ripple-blanking output (if low, blanks all outputs)
  • Pin 3--lamp test (logic 0 turns on all segments)

(Note--The outputs of the 7446 can pull down very high currents, up to 40.mA. These outputs are open collectors so as to permit running their loads from a separate power supply of up to 30 V. LED'S driven by the system have their anodes tied high, and their cathodes go through current-limiting resistors to the outputs of the chip. Because of the extremely high current-drain needed to illuminate several digits, "blanking" features are provided. 0's off either end of a number can be suppressed by connecting the "ripple-blanking input" of each chip to the "ripple-blanking output" of its neighbor, and grounding the "ripple-blanking input of the left most chip. Grounding the "ripple-blanking output" of any chip causes suppression of all outputs, regardless of the information on its BCD inputs.)


(Seven segment BCD decoder):

  • Pin 9--Ground
  • pin 18--VCC
  • pin 15--a in
  • Pin 16--b in
  • Pin 17--c in
  • Pin 1--d in
  • Pin 2--e in
  • Pin 3--f in
  • Pin 4--g in
  • Pin 7--A out (least significant bit)
  • Pin 8--B out
  • Pin 10--C out
  • Pin 11--D out (most significant bit)
  • Pin 6--output enable (0 enables outputs, 1 puts them in tristate)
  • Pin 14--inverting/non-inverting input control (logic 1 selects active low decoding)
  • Pin 12--latch enable (1 latches outputs, 0 permits flow-through)
  • Pin 13--minus out (goes to 1 for an input of g alone)
  • Pin 5--error output (goes to 1 for a non-standard input)

(Note--This versatile decoder has been programmed to recognize all the 7-segment exceptions discussed in the text; a "1" can either be b and c or e and f etc. An input signal of "g" alone is taken as "minus" and is indicated by a logic "1" on pin 13, the "minus output". An "error" signal from pin 5 indicates that something non-standard has been impressed on the inputs. These inputs can be brought above VCC, making the chip ideal for interfacing various diode illumination signals with devices requiring 5V logic levels. Pin 14, the inversion control pin, tells whether a high or a low input signal is to be considered as a segment "on". Although CMOS, the outputs of this decoder can pull down the necessary 1.6ma required to drive one TTL input. These outputs can become tristate, i.e. they can be connected by bringing in pin 6 "output enable" to a logic "1". Worthy of mention is that an "error" input automatically puts the outputs into the tristate condition. Finally, this device has a "latching" feature. Grounding pin 12 allows normal flow-through of data. Bringing pin 12 to a logic "1" holds the output information steady while changes on the inputs are ignored. Latching is very important for holding and preparing 7-segment display readings to be announced by speech boards).


Technical Innovations Bulletin (TIB) A stereo cassette quarterly periodical is now available from Innovative Rehabilitation Technology Inc. (IRTI, 375 Distel Circle, Suite A 11., Los Altos, CA 94022, Tel.415/965-8102.)

The purpose of this entertaining PIB is to inform the listening audience of technological trends and vocational aids. Much of this material is presented by way of live interviews with those who benefit from the technology and those responsible for its development. The first issue includes interviews with a blind computer programmer, a radio engineer, and a research engineer, Bill Gerrey, editor of SKTF. Whenever possible, we attempt to demonstrate products in sound.

We view this TIB as being supplemental to the highly technical information provided by the Smith-Kettlewell Technical File. Our TIB discusses practical applications of commercial products and assistive devices.

This year's (1981) two issues of TIB plus all other cassette brochure materials are available for $6.00.


All right! You asked for it, you got it! A tremendous amount of interest has been expressed in material on digital logic. As a responsible editor I felt under pressure to put such material together; we'll have to know this stuff for making talking instruments. Based on the fundamentals in this issue, future issues will bring you many articles focusing on applications of digital electronics.

I made a couple of false starts myself, but nothing I wrote sounded very good. Out of the blue, a reader named David Plumlee asked, would I mind if he contributed a paper or two on digital logic projects. In answer to my cries for help, Mr. Plumlee sent along nearly 70 typed pages of fine material on the subject, starting with "Wire Wrapping" (spring 1981). (Accompanying the first few dozen pages of his manuscript was a letter saying, "I have never written technical material before,...") I was so inspired by his work that I loosened up and wrote three short papers on related subjects for this issue ("Inside Gates", "Flip-Flops", and "Counting in Base 2").

Not only is he a prolific writer, but he's a confirmed tinkerer, and I'm sure you will enjoy his material as we run it in SKTF.

When I started this magazine, I promised both you and its sponsors "pie in the sky". I spoke of unsung role models and untapped engineering talent that lay beyond a gap in communications, not beyond the abilities of visually handicapped people. Is our system working?

So far, we have tapped the problem solving engineering mind of Bob Gunderson for his diode checker (fall 1980) and for circuits of important instruments from his previous work. We have been treated to the teaching abilities of David Plumlee, bringing us into the world of digital electronics. Surveys of important test equipment (both old and new) have brought to our attention the contributions of other blind people whose work has already enriched the pages of the Braille Technical Press. Much more of the same material is already in hand.

This fine publication has found its way into nearly a dozen countries of the world. 14 percent of our subscribers are outside of the US.

We have shown our "pie in the sky" to be based on the sound principle of self help.

The board members of the Smith-Kettlewell Eye Research Foundation have shown their faith in this concept by contributing considerable seed money to this endeavour. Like any seed, growth will come from that which is new; we must ensure solidity of this structure by promoting its concept and by increasing our subscribership. You, by demonstrating the powerful effect of self-help, have created a base from which a strong independent structure can grow. Please, spread the word, tell a friend, and keep the short-wave bands buzzing with the message that our independence rests in our own resourcefulness.

In the meantime, let the handicapped community at large take pride in the fact that "pie in the sky" tastes awfully sweet to those who have actively taken command of their utensils.