SKTF - Fall, 1981

The Smith-Kettlewell Technical File

A Quarterly Publication of The Smith-Kettlewell Eye Research Institute’s Rehabilitation Engineering Research Center

William Gerrey, Editor

Issue: SKTF - Fall, 1981

Original support provided by: The Smith-Kettlewell Eye Research Institute and the National Institute on Disability and Rehabilitation Research

Note: This archive is provided as a historical resource. Details regarding products, suppliers, and other contact information are original and may be outdated.

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This discussion is intended to serve as yet another example of how digital devices are used, and it should remove some of the mystique surrounding the complicated instructions provided with the S2 series of mini speech boards (see Fall 1980).

Dispelling Confusion

Nowadays, technical literature is fraught with acronyms and abbreviations. The engineering notes on the mini speech boards are no exception. A few turns are uncloaked in the paragraphs below.

Much ado is made over a doodad called the "CRC" which is heralded as the paragon of microcircuits. We are told that "CRC" stands for "microcontroller", and we are left to assume that perhaps this is the case in Flemish or Esperanto. Suspecting that the term "CRC" had English roots, I called my consultant at TSI, Richard Oehm of the Service Department who informed me that CRC stands for "Custom ROM Controller". All this chip does is look at the input lines and leaf through appropriate file cabinets in the memory chip which instructs it how to speak. TSI had the CRC chip grown in a manufacturing plant to do only this one specific job; we would have no use for this component in salvage. Other than hoping that it keeps working, we don't care what its "house name" is how it goes about its business.

An occasional piece of information in the Table of Characteristics comes in handy. For example, this table tells us that the "START" must be a minimum of 2 microseconds in duration, "tSW--START Pulse Width, 2 u Sec. min." If we were to use a one-shot to trigger the speech board, we would choose a resistor and capacitor to give us 2 uSec. or longer. For example, the formula for calculating the time presented by a one-shot CD4098 is, t= .5 times Rx times Cx, and we are told that we must restrict the values; the resistor must not be less 5K, and the capacitor must not be less than .01uF. For trial and error purposes we plug these values into the 4098 formula, t=.5 times 5K times .01uF = .000025 seconds, or 25 microseconds. Therefore, the shortest time we can achieve with the 4098 is longer than that needed to trigger the speech board. Other terms in the table may never tickle our fancy; for example, the speech delay time (tSD) will be no longer than 120 uSec. At least we won't fall asleep waiting for it to talk.

Confusion reigns supreme over the power supply requirements of the board. The way the chips were manufactured, they run on negative voltages. Anything we are likely to find at Radio Shack to drive the boards will give us logic at positive voltages. Therefore, we must forget about what TSI calls ground for these boards and choose another voltage reference which we can call "ground" instead. We shall rewrite the power supply connections to the board as follows:

Pin 9 is grounded. Pins 1 and C go to plus 5 volts (pin C is something TSI uses for testing, we'll just do what we're told and tie it to pin 1). Pin L goes to minus 10 volts. A suitable power supply appears in section 1.0 of the next article.

Inputs and Outputs

These boards have 7 inputs and 2 outputs. Of the 7 inputs, 6 are used to feed the board a binary number, and each combination of 1's and 0's makes the board say something different. These are called the "address" or "data" lines (SA lines). The seventh input "triggers" or "STARTS" the board; in other words, the board won't even look at the data lines and speak until a signal on this "START" input tells it to do so.

One of the outputs is the "Audio Analog Output" (AAS), which feeds into an amplifier and speaker system. A circuit for an appropriate amplifier appears in section 3.4 of the next article.

The other output called the "BUSY" line, is something you may or may not need to use. You can use this output to notify your driving circuitry when the speech board has been triggered and is talking. In our talking voltmeter of the next article, this line is used to advance the driving circuitry so as to feed the board new information. Whatever this line signifies to your circuit, the principle of using it is called "handshaking" in the computer field. Your driving circuit shakes the START line of the speech board, whose BUSY line squeezes the hand of your circuit until the one-word speech is over.

Address Codes

The 6 SA lines are to be presented with a 6-bit binary number called an address code. Before the speech board is "STARTED", a number must be impressed on these inputs to tell the board which word in its vocabulary is to be spoken.

Suppose we tie all the address lines to ground; we have presented the board with an address code of 000000. Triggering the "START" line will now cause the board to say "oh." If we tie pin 7 to plus 5V and leave the other lines grounded (an address code of 000001), triggering the board will cause the board to say "one."

Demonstration Hookup

Just to hear our board talk, let's connect its inputs to switches so that we can manually address its vocabulary. We shall connect each of the 6 data inputs to the arm of its own single-pole, double-throw toggle switch. The downward positions of all 6 switches are grounded, and their upward positions go to plus 5V. Any switch in the upward position presents its data line with a logic 1; switches which are down represent a logic 0.

To trigger the board, we'll connect the "START" input to the arm of a single-pole, double-throw pushbutton switch. The normally closed contact is grounded, and the normally open contact goes to plus 5 V.

Pushing the "START" button brings this line to a logic 1, at which point the "BUSY" output waves a flag to tell us that the speech board has gotten the message. (Note that the "BUSY" line goes from a logic 1 way down to minus 10 V when triggering has occured.) Releasing the button initiates speech (except for the "BUSY" line, the board is "negative- edge triggered").

After the word has been spoken, the "BUSY" line drops the flag (Goes back to a logic 1) and waits for the next "START" pulse.

Say "Please"

Given our lineup of toggle switches how do we make an S2B unit say the word "please." We look up the address code for "please" in appendix 2 (see Fall 1980). This code is listed as the decimal number 047 (forty- seven). We note that 47= 32 + NOT 16 + 8 + 4 + 2 + 1, which corresponds to the binary number 101111. Therefore, using our array of toggle switches, we ground pin F and flip up pins 5,H,K,8 and 7. Now push the "START" button--please.

Doorbell for the Conspicuous Consumer

For the bloke who has everything, our "please" machine could serve as a doorbell. As an illustrative project, let's make a fancier talking doorbell that says "plus" for the front door and "minus" for the back door.

Each doorbell button must have access to a selection of appropriate data inputs. For this project, it would be nice if two isolated sets of duplicate input lines were available. We can accomplish this by driving each data line with a 2-input OR gate. We will use the A inputs of the OR gates for the front door, and their B inputs for the back.

Consulting the revised version of Appendix 1, we see that an S2A will speak the word "plus" when presented with an address code of 22 (010110), and the word "minus" can be addressed by the code 21 (010101).

For the front door, the first, third and sixth input lines (the A inputs of these OR gates) are tied permanently to ground, and the second, fourth and fifth inputs go to the button.

For the back door, the first, third and fifth B inputs are grounded, while the second, fourth and sixth go to the button. Note that of the two numbers 010110 and 010101, only the last two digits differ from each other; the first four OR gates can be dispensed with and these S2A lines can be permanently tied to their respective logic levels.

In addition to presenting the address codes, we need a way of "START'ing" the speech board. We can use a one-shot (set up for leading-edge triggering) to send a quick "START" pulse to the board as soon as the button is pressed. Once again, since the two buttons must feed into isolated inputs, we will use two such one-shots with their Q outputs being combined in an OR gate whose output goes to the "START" line of the S2A.

The doorbell button must go from a logic 0 to a logic 1. Where do we get single-pole double-throw doorbell buttons? We can make a simple normally- open switch do the job of its fancier counterpart by doing the following:

We will cause the operable inputs (those which go to the button) to "rest" at ground by pulling them to ground with a resistor, a "pull-down" resistor. (A pull-up resistor would go to a logic 1-- this one pulls the inputs to a logic 0.) The simple push button can then go from the top of the pull-down resistor up to plus 5 V. The value of this resistor can be anything, the speech board instructions talk in terms of 5.6 K.

Back to the Drawing Board

Suppose in building this device, we were to find that the words spoken were not consistant or we had other signs of trouble. Could it be that our well- thought-out project has a design flaw? Although I don't see a hint of it in the instructions, perhaps we need to establish the data information on the address lines before we send the board a "START" pulse. As it stands now, pushing the button will do both simultaneously. We can cascade one-shots to buy a little time; the one-shots from the buttons are combined in their OR gate whose output triggers a third one-shot which triggers the board.

In the Table of Characteristics, the engineering notes list a figure for the minimum "Data Present Time" (tDP) of 140 uSec. If your caller has a very quick finger, or if contact bounce interrupts presentation of the data, we cannot be responsible for what the board says. Perhaps for the sake of engineering elegance, we shall present this data through a one-shot which can hold it on the inputs for 140 uSec beyond the conclusion of the "START" pusle. The "START" pulse can be very short, we'll make it 25 uSec. If 2 one- shots are cascaded, as in the previous paragraph, we have 50 uSec. accounted for beyond which time the data must hang in there for an additional 140 uSec. Using 4098's, the START one-shots can have Rx = 5K and Cx = .01uF. The data one-shots need to have ten times this delay time, we'll make Cx = .1 uF.

The Vice President in charge of production comes to us complaining that inverting gates are more commonly available than noninverting ones--why did we have to use OR gates? We can satisfy him by using NAND gates on the input lines. As per statement 1 of De Morgan's theorum, NAND gates will work if we invert the inputs (the doorbell must go from a logic 1 to a logic 0 when pressed). To accomplish this inversion, one side of the button is grounded, and the other side goes through a pull-up resistor to plus 5 V. The START one- shots will now have to be set up for negative-edge triggering, and their Q bar outputs will be combined in a NAND gate (thus taking care of the necessary logic inversion on the NAND inputs).

Why spend all this time on one speech product over all the others? First, the S2 series has been used in so many products and prototypes that much engineering has already been done, the results of which are available as circuit diagrams. Second, the TSI S2A and S2B boards understand BCD; they give us numbers when four of their input lines are so addressed. Third, they are essentially simple, and the principles of their use can be extended to include other fixed-vocabulary systems. Now that these principles have been set down so "clearly???" we can let those who wish to experiment proceed in doing so while the rest of us leave this boring digital stuff alone for a while.


by Albert Alden

[Abstract by the editor

A number of 3-1/2 digit multimeters used the Intersil ICL7100 series voltmeter chip to convert an analog unknown voltage into a visual read-out of 7-segment numerals. The "talk box" to be described is specifically designed to read the LED-driving version of this voltmeter chip, the ICL7107. Although not specifically detailed here, the method whereby a talk box could be built for the liquid-crystal version, the ICL7106, is indicated.

A commercial voltmeter using the 7107 can be converted for voice read-out by building this talk box as a separate unit, or a self-contained meter can be built from scratch by using the 7107 as a component.

This design satisfies the essential criterion that readings on the visual display are instantaneously sampled and "latched", whereupon they are subsequently spoken as an entity. I have evaluated talking instruments of a simpler design whose digits are spoken as they are individually sampled. With these simpler instruments, noise and/or dynamic information on the unknown quantity lead to readings, which are completely erroneous--for example, a quantity drifting around 49 or 50 will cause these devices to say, "four nine, five oh, five nine, four oh." In the editor's view, these simpler designs should be rejected as unsuitable.]

Credit must be given to Taylor Davidson at the Bureau for the Blind of Kentucky who, under the direction of Dr. T.V.Cranmer, designed a voice output system for a digital multimeter manufactured by the John Fluke Co. While changes were made to simplify his original design, such as choosing the ICL7107 over the 7106, major portions of his work remain.

The talkbox built here is a separate unit designed to accompany a commercial meter, the Nonlinear Systems "Touch Test 20", available from Fordham Radio * for about $ 400. This meter's features include capacitance measurement, a built-in audible continuity tester, and a thermometer probe. Its front panel contains many controls of the type called "touch switches"; the blind user may wish to run strips of tape between the rows and columns of these switches to mark their positions. Our associated talkbox is built into a Bakelite cabinet measuring 7-1/2 by 8-1/2 by 3 inches. The front panel of the talk box contains an on-off switch, a "run" switch (to initiate speech), a volume control, and a "word rate" control.

Although the Touch Test 20 is battery-operated, no attempt was made to run the talkbox on battery power. If use of this meter above ground in high- voltage circuits is intended, suitable insulation must be included in the construction of the talkbox to protect the user, and a power transformer capable of withstanding this stress must be used in its power supply.

A 26-wire cable is used to connect the talk box to the various elements of the visual display. A 25-pin connector (Jameco DB25P and DB25S, plug and socket, respectively, available from Jameco * ) is used for the interconnection between the two units. The shell of this connector is used to make the ground connection (the 26th wire). Care must be taken to avoid this connector shell when high voltages are present.

The voice output is controlled by a "run" switch. When this switch is open, the talk box is in standby. Closing the switch initiates cycling of the speech system, and readings will be continually presented until this switch is re- opened. Opening this switch during a reading does not immediately terminate speech, presentation of the full display will run its course before the system comes to rest in a standby condition. Therefore, if desired, a normally open momentary "run" switch can be included so that the user can obtain a single reading with the push of a button.

A "beep" is presented by the voice output system to punctuate the end of each reading. In this way, the user can easily distinguish one reading from the next.

Preliminary discussion of circuit operation

The 6 address lines of the S2A Mini Speech Board are sequentially presented with information which is decoded from the visual display. Seven- segment digits are converted to BCD (using National Semiconductor MM74C915's) and presented to the four address lines SA2 through SA5 of the S2A. Features of the 74C915 decoders include the ability to "latch" and hold data to be presented. Other aspects of the visual display, such as the minus sign, decimal points, and the initial digit "one", are decoded and presented to the S2A address lines via hard-wired logic.

The address codes of the speech board are such that the 4 least significant data lines must be "shared" among the BCD outputs and the other hard-wired logic. Tri-state devices are used to control these lines so that their outputs can be "enabled" for presentation to the board one set at a time. When outputs of "disabled" circuits are in the tri-state condition, they are effectively disconnected, and will have no effect on "enabled" outputs. (For an explanation of tri- state devices see "Gabbing about Gates", SKTF, summer 1981.)

Information from the various display-decoding circuits is "gated" to the speech board by a sequencing device termed the "commutator" in the circuit description. This sequencer is a so- called "one-of-eight decoder" (CD4022); one each of eight outputs goes high in sequence as dictated by a clock signal.

A triggering signal to advance the commutator is derived by sensing the conclusion of each event--the end of a spoken word or the detection of a "blank" on the display.

[Editor's comment

Except for connecting bypass capacitors, pull-up resistors, and building the audio amplifier, this project is ideal for wire-wrapping. To avoid trouble- shooting, I recommend soldering .1 uF capacitors across the supply pins of each chip near the bottom of the wire- wrap posts; wire-wrapping can procede above these solder connections. The pull-up resistors on the BCD lines can be soldered to the S2A edge connector. The LM386 amplifier circuit must be built using point-to-point or other wiring techniques, since it has many external components. (For a discussion of wire-wrapping, see SKTF, spring 1981.)]

(1.0) Power Supply

The S2A speech board requires voltages of +5 and -10 Volts. A dual supply was constructed in our talk box to provide these two voltages. However, if the ICL7107 voltmeter chip is included as a component of this project, an additional -5 Volt supply must be provided (the 7107 operates on + and - 5 Volts).

1.1) Power supply circuit

A 24V transformer with a center tap is used to derive + and - voltages to be presented to the inputs of appropriate voltage regulators. The 117V primary has one side going through a fuse (.25 Amp, slow-blow), then through a switch (SPST) to one side of the AC line. The other side of the primary goes to the other side of the AC line.

The center tap of the 24V secondary is grounded. For the positive supply, each end of the secondary goes to the anode of a diode (1N4001); the cathodes of these two diodes are connected together and are bypassed to ground through 250 uF (negative of the capacitor on ground). For the negative supply, each end of the secondary goes to the cathode of a diode (1N4001); the anodes of these two diodes are connected together and are bypassed to ground through 250 uF (positive of this capacitor on ground).

The junction of the first two diode cathodes and its bypass capacitor goes to the input terminal of a Fairchild uA7805, with the common terminal being grounded. The output of the 7805 is bypassed to ground through .01 uF, and this output is the +5V line.

The junction of the second two diode anodes and their bypass capacitor goes to the input terminal of a uA7908, with the common terminal of this 7908 going through 56 Ohms to ground. The output, which becomes the -10 V line, goes through 270 Ohms to the junction of the regulator's common and the 56 Ohm resistor. The 270 Ohm resistor is shunted by .01 uF.

If the 7107 is to be operated from this supply, the anodes of the second two diodes also go to the input of a uA 7905, with the common terminal of this regulator being grounded. Its output, the -5 V line, is bypasssed to ground through .01 uF.

1.2) Speech board (S2A) supply connections

Pin 9 of the speech board is grounded. Pins A and C are tied together and go to + 5 V. Pin L goes to -10 V. (To prevent noise from entering the supply lines of the board, TSI recommends that bypass capacitors be attached at the edge connector. No such capacitors were used in our talkbox.)

1.3) Peripheral Circuit Supply connections

Good practice dictates that several lines supplying small groups of chips should be run so as to branch off from main supply buses, as opposed to stringing together all the supply terminals and running a single lead over to the power supply. For example, IC's 1, 2 and 3 can have their supply terminals wired together, and then a lead can be run from one of these over to a heavier bus bar. In addition, bypass capacitors can be installed on or nearby these groups as preventive medicine.

In addition to listing supply terminals, other necessary VCC and ground connections on the chips will be listed, for example, pins 13 and 15 of IC4 are tied to VCC because they are enable and reset terminals.

The following pins are grounded: pin 9 of IC's 1,2 and 3; pins 8,13 and 15 of IC4; pin 7 of IC's 5 and 6, pins 11 and 13 of IC6; pin 7 of IC's 7 and 8; pins 2,4,6,8,10,12 and 14 of IC's 9 and 10; pin 7 of IC11; pins 7 and 5 of IC12; pin 8 of IC's 13 and 14; pins 2 and 4 of IC15.

VCC connections are: pins 14 and 18 of IC's 1,2 and 3; pin 16 of IC 4; pin 14 of IC's 5 and 6; pin 14 of IC's 7 and 8; pin 16 of IC's 9 and 10, pin 1 of IC 10; pins 9 and 14 of IC11; pin 14 of IC12; pins 3,5,11,13 and 16 of IC's 13 and 14; pin 6 of IC15.

(2.0) Input System

A full discussion of the 7107 voltmeter chip appears in section 6. With regard to interfacing the talkbox with various meters, the following points should be considered:

In the liquid crystal version of the Intersil chip (7106), both the character segments and their backplane are "strobed"; the segments cannot be decoded simply by treating their outputs as "active-high" or "active-low". Segments which are off are in phase with the backplane, while those which are on are out of phase with the backplane. To detect segments which are on, each segment output can be fed to the A input of an "exclusive OR" gate. The B inputs of all the OR gates go to the backplane. In this way, segments out of phase with the backplane produce a logic 1 output from the OR gates. In the adapted Fluke meter of Taylor Davidson's design, seven 4070 quad 2-input exclusive OR gate chips were needed to accomplish this.

The outputs of the above OR gates present suitable signals for "active- high" decoding; the inverters of IC6 are no longer necessary in the Talkbox, and the inverting/noninverting terminal of the decoders (pin 14 of IC's 1,2 and 3) must go to ground instead of VCC.

The interface connections between the Talkbox and commercial meters could be greatly simplified by building a voltmeter chip inside the Talkbox and using a single coaxial cable to couple the analog signal from the meter to the self-contained speech output system. However, decimal point signals are not gotten from the voltmeter chip--rather, they are derived from range-switching circuitry of the multimeter.

2.1) 74C915 Seven-Segment to BCD Decoder Connections

All three 74C915's (IC's 1,2,and 3) have their "inverting/non-inverting" terminals (pin 14) tied to plus 5V to select active-low decoding.

As mentioned in 4.1.1, the "latch enable" terminals (pin 12) of the 74C915's are tied together; they get their signal from an inverter (IC5, 4069; pin 12 out, pin 13 in), with the inverter's input going to the "0" output of the commutator (4022, IC4).

2.1.1) 74C915 Outputs

The BCD outputs are connected in parallel; the "D" outputs of IC's 1,2, and 3 are tied together (pins 11, most significant bit) the "C" outputs of IC's 1,2 and 3 are tied together (pins 10), the "B" outputs are tied together (pins 8), and the "A" outputs of 1,2, and 3 are tied together (pins 7, least significant bit). As mentioned in 3.1.1, these outputs go to the data input lines of the S2A speech board.

As mentioned in 3.1, pull-up resistors (going from these lines up to 5V) are needed to establish a logic "1" on these lines when outputs are in the tri-state condition.

2.1.2) 74C915 Inputs

The seven segments of each visual digit feed into corresponding inputs of its decoder chip. The numbering system of the segments and the corresponding 74C915 pin numbers are listed below:

Starting from the top-most segment and moving around the perimeter clockwise, the bars are denoted a, b, c, d, e, and f, with g being the bar across the center digit. The corresponding inputs to a 74C915 are 15,16,17,1,2,3, and 4, respectively.

2.2) "Minus", "One", and "Point" Signals

These signals are inverted and then NAND'ed with the appropriate outputs of the commutator (IC4, 4022), and their information is then fed to the "Enable" pins of the appropriate tri- state buffers (see 4.1.1, 4.1.2, and 4.1.4).

2.2.1) "Minus"

The "minus" signal goes through an inverter (IC6,4069; pin 1 in, pin 2 out) to the pin 1 input of a NAND gate (IC7, 4011; pins 1 and 2 in, pin 3 out); the other input (pin 2) of this NAND gate goes to the "1" output of the commutator (pin 2 of IC4). (Note that this "1" output also latches the 74C915 decoders, see 2.1 and 4.1.1).

2.2.2) "One"

The first digit of this visual display is a single vertical bar "one", rather than being a seven- segment character. This "one" signal goes through an inverter (IC6; pin 3 in, pin 4 out) to the pin 12 input of a 4011 NAND gate (IC8; pins 12 and 13 in, pin 11 out) ; the pin 13 input goes to the "1" output of the commutator (pin 1 of IC4). (It is purely a coincidence that the "one" signal is gated by the "1" output of the 4022.)

2.2.3) "Point"

Although three decimal points exist on the visual display, trouble is taken to sense only two of them; the third of these appears after the last digit, and was therefore thought to be pointless. The two decimal points used appear between full seven-segment digits.

The first "point" goes through an inverter (IC6, 4069; pin 5 in, pin 6 out), then to the pin 9 input of a 4011 NAND gate (IC8); the pin 8 input goes to the "3" output of the commutator (pin 7 of IC4).

The second "point" goes through an inverter (IC6; pin 9 in, pin 8 out), then to the pint 6 input of a NAND gate (IC8); the pin 5 NAND input goes to the "5" output of the commutator (pin 4 of IC4).

Since the same of tri-state buffers (IC10, see 3.1.2) set up the "point" address lines of the speech board, the two "point" signals derived above must be combined in a third gate so that either "point" signal may operate the single "Enable" pin of the tri-state buffers. The outputs of the first two NAND gates (pin 10 and pin 4 of IC8) go to pins 1 and 2 of the third gate (all on the IC8 chip).Pin 3, the output of this NAND gate, goes through an inverter (IC5, 4069; pin 9 in, pin 8 out), then to the "Enable" of the buffers (pin 15 of IC10).

(3.0) Connections to the S2A

3.1) Data Inputs

In order of their significance, the six data inputs are:

  1. SA0--pin 5 (most significant bit)
  2. SA1--pin f
  3. SA2--pin h
  4. SA3--pin K
  5. SA4--pin 8
  6. SA5--pin 7 (least significant bit)
3.1.1) BCD Inputs

Pins H,K,8, and 7 (SA2 through SA5) go to the D,C,B,and A outputs of the 74C915's, respectively. Specifically, the "D" outputs (pins 11 of IC's 1,2 and 3) are tied together and go to H of the S2A. Pins 10 of 1,2, and 3 go to "k" of the S2A. Pins 8 of 1,2 and 3 go to pin 8 of the S2A. Finally, pins 7 of IC's 1,2 and 3 go to pin 7 of the S2A, the least significant bit.

These four inputs to the S2A require pull-up resistors to plus 5V (10K resistors were used here).

3.1.2) "Minus", "One", and "Point" Addresses

The address lines for "minus","one" and "point" are partially controlled by tri-state buffers. (By "partially", it is meant that the SA1 and SA0 lines are operated differently and are discussed later in this section, as well as in 4.1.5)

The tri-state devices used are CD4503's or MM80C97's, and appear as IC's 9 and 10 in our circuit.

All 4503 inputs are grounded (pins 2,4,6,10,12 and 14 of IC's 9 and 10). Appropriate address lines going to these buffers' outputs are taken to a logic 0 (shorted to ground) when the buffers are taken out of the tri-state condition.

Outputs 3,5,7 and 9 of the 4503's are "Enabled" using pin 1. Outputs 11 and 13 are "enabled" by pin 15. A logic 1 on an "enable" pin puts its buffers in tri-state; the buffer outputs are "enabled" by a logic 0.

Buffer outputs 11 and 13 of IC9 go to S2A pins H and 8. The "Enable" pin 15 goes back to the output (pin 3 of IC7), the NAND gate combining the inverted "minus" signal with the "0" output of the commutator (see 2.2.1 and 4.1.1)

Outputs 3,5 and 7 of IC9 go to S2A pins H,K and 8. The "Enable" pin 1 goes back to the output (pin 11 of IC8), the NAND gate which combines the inverted "one" signal with the "1" output of the commutator (see 2.2.2 and 4.1.2).

The 11 and 13 outputs of the second 4503 (IC10) go to S2A inputs H and K. The "Enable" pin 15 is controlled via an inverter (IC5, 4069; pin 9 in, pin 8 out), with this inverter's input going back to the NAND gate output (pin 3 of IC8) which presents both "point" signals. (see 2.2.3 and 4.1.4).

The SA1 input (pin F) is controlled directly by the output of a 4-input NAND gate (IC11, 4012; pins 9,10,11,12 in and pin 13 out). Only three inputs to this gate are used; the unused input (pin 9) is tied to plus 5V. The pin 10 input goes to the "Enable" of the "minus" buffers (pin 15 of IC9), the pin 11 input goes to the "Enable" of the "point" buffers (pin 15 of IC10), and the pin 12 NAND input goes to the output of an inverter whose input goes to the "beep" or "7" output (pin 10 of the commutator (the inverter is IC5, 4069; pin 10 out, pin 11 in). (The above is restated in 4.1.5) Once again, this 4- input NAND gate's output (pin 13) goes directly to pin F of the S2A.

In other words, the SA1 line is brought to a logic 0 by the 4-input NAND gate during every address except "minus", "point" and "beep", at which point a low input to the NAND gate causes its output to raise SA1 to a logic 1.

Finally, as restated in 4.1.5, the SA0 input (pin 5 of the S2A goes directly to pin 10 of IC4, the "7" output of the commutator. This is done to generate a "beep" to signify the completion of a display reading.

3.1.3) Blank detector

A 4-input NAND gate is set up to determine when no meaningful address has been presented to the S2A input lines. When a "blank" is detected by the NAND gate, the timing circuit is set up to advance rapidly until meaningful information again appears on the address lines.

The other half of IC11, the dual 4- input NAND gate, is used (IC11, 4012; pins 2,3,4,5 in, pin 1 out). Input pins 2,3 and 4 go to S2A pins H,K and 8 (SA2,SA3 and SA4); the pin 5 NAND input goes to the inverted "beep" signal (it goes to inverter output pin 10 on IC5).

Pin 1 of IC11 is the output of the blank detector. As restated in 5.2.2, this "blank detector" gates pulses from the Q bar output of FF3 back to the input of the timing circuit; the pin 1 output of IC11 goes to the pin 3 input of a 3-input NOR gate IC12. IC11's output also goes to the "Clear" terminal of FF2 (pin 13 of IC13) so as to interrupt the "START" pulses to the S2A.

3.2) "START" Input

As stated in 5.2.3, the S2A "START" line (pin 6) is operated by the Q output of FF2 (pin 10 of IC13). The triggering time of FF2 is slightly delayed from that at which the visual display is sampled; this assures that the desired information is present on the data lines before the speech board is "START'ed". This delay is taken care of by FF1.

3.3) "BUSY" Output

The "BUSY" line of the S2A swings from plus 5 to minus 10 volts; a diode clamp must be included to limit the swing of this line to 5V. The "BUSY" output (pin D) of the S2A goes through a 1N914 diode (anode toward pin d) then through a 10K resistor to ground. The junction of the cathode and the resistor is the "compatible BUSY output".

As stated in 5.2.3, the "compatible BUSY output" goes to the trigger of FF4 (pin 12 of IC14). The Q output of FF4 is used to initiate another cycle in this array of one-shots (provided no "blanks" are detected). FF4 provides a space between words of the speech board, and the length of this space can be adjusted with the "word-rate control".

3.4) Audio Amplifier

The speech board audio output (pin J) goes through 1uF (positive toward pin J), then through two 18K resistors in series to the top of a volume control (10K ohms). The bottom of this control is grounded. The junction of the two 18K resistors goes through .005uF to ground. The volume control is shunted by .02uF. The arm of the control goes to pin 3 of an LM386 amplifier chip (IC15).

Pins 2 and 4 of the LM386 (IC15) are grounded. Pin 6 goes to plus 5V, and pin 6 is bypassed to ground by 250uF (negative end at ground). To stop oscillations of the amplifier (which manifest themselves as "raspyness" of the output), the output (pin 5) goes through 0.22uF to pin 4 and ground. If the oscillations persist, bypass pin 7 to ground through 25uF (negative at ground). If oscillations still occur, connect a 0.01uF capacitor with very short leads between pins 2 and 3 (across the inverting and non-inverting inputs).

(4.0) Commutator (CD4022, "One-of-Eight Decoder")

As pulses trigger the input terminal of this 4022 chip, the eight outputs (denoted "0" through "7") go high and then go low again in sequence. Using this chip, information from the visual display is sequentially "gated" through to the speech board. This 4022 appears as IC4 in the circuit.

4.1) Commutator Output connections

The eight outputs are listed below:

  • pin 2--"0"
  • pin 1--"1"
  • pin 3--"2"
  • pin 7--"3"
  • pin 11--"4"
  • pin 4--"5"
  • pin 5--"6"
  • pin 10--"7"
4.1.1) "0" Output

The "0" output performs two functions; it latches all three 74C915's (IC's 1,2 and 3), and it gates the "minus" signal through to the speech board (as stated in 2.2.1 and 3.1.2).

The "0" output (pin 2 of IC4) goes to the input of an inverter (IC5, 4069; pin 13 in, pin 12 out), and the output of this inverter goes to the "Latch Enables" of the 74C915's (pins 12 of IC's 1,2 and 3).

This "0" output also goes to the pin 2 input of a 2-input NAND gate (IC7, 4011); the pin 1 NAND input gets the "minus" information through an inverter (IC6, 4069; pin 1 in, pin 2 out). The NAND gate output (pin 3) goes to the "Enable" pin 15 of IC9, the "minus" buffers.

4.1.2) "1" Output

This output gates the "one" information of the display through to the speech board. (It is purely co-incidence that the "one" information is controlled by the "1" commutator output.)

The "1" output (pin 1 of IC4) goes to the pin 13 input of a NAND gate; the pin 12 input gets the "one" information through an inverter (IC6, 4069; pin 4 out, pin 3 in). The output of the NAND gate (pin 11 of IC8) goes to the "Enable" (pin 1) of the "one" buffers (IC9). (The above is restated in 3.1.2 and 2.2.2)

4.1.3) The "2","4" and "6" seven- segment to BCD Outputs

These outputs "Enable" input decoders IC1, IC2, and IC3. (A logic "0" "enables" the decoder outputs.)

The "2" output of the 4022 (pin 3) goes through an inverter (IC5, 4069; pin 1 in, pin 2 out), with the inverter output going to the "Enable" (pin 6) of IC1.

The "4" output (pin 11 of IC4) goes through an inverter (IC5, 4069; pin 3 in, pin 4 out) to the "Enable" (pin 6) of IC2.

The "6" output (pin 5 of IC4) goes through an inverter (IC5,4069; pin 5 in, pin 6 out) to the "Enable" (pin 6) of IC3.

4.1.4) "3" and "5" outputs

These outputs each gate a "point" signal through to the speech board (see 2.2.3 and 3.1.2).

The "3" output (pin 7 of IC4) goes to the pin 8 input of a NAND gate (IC8, 4011); the other NAND input (pin 9) comes from an inverter (IC6, 4069; pin 6 out, pin 5 in), with the input of this inverter going to the first "point" of the visual display.

The "5" output (pin 4 of IC4) goes to the pin 5 input of another NAND gate (IC8); the pin 6 input of the NAND gate comes from an inverter (IC6, 4069; pin 8 out, pin 9 in), with the inverter input going to the second decimal "point" on the display.

The outputs of the above two NAND gates (pin 10 and pin 4 of IC8) go to inputs 1 and 2 of the same chip (another 2-input NAND gate). The output of this latter NAND gate (pin 3) goes through an inverter (IC5, 4069; pin 9 in, pin 8 out), and the output of the inverter goes to the "Enable" (pin 15) of the "point" buffers (IC10) (see 3.1.2).

4.1.5) "7" Output

This output provides the "beep" address to the SA0 line; it also signals the timing circuitry that a complete "reading" has been completed. (see 3.1.2)

The "7" output (pin 10 of IC4) goes directly to the SA0 input (pin 5) of the S2A.

The "7" output also operates the SA1 line indirectly, pin 10 of IC4 goes through an inverter (IC5; pin 11 in, pin 10 out), with the output of the inverter going to one of four inputs of a 4-input NAND gate (IC11, 4012). The pin 11 NAND input goes to the "Enable" of the "minus" buffers" (pin 15 of IC9). The pin 10 NAND input goes to the "Enable" of the "point" buffers (pin 15 of IC10). The pin 9 input of the NAND is unused and is tied to plus 5V. The NAND output (pin 13 of IC11) goes to the SA1 line (pin F) of the S2A. (The above is restated in 3.1.2)

(5.0) Timing Circuitry

An array of four one-shots, FF1 through FF4, is set up to "clock" the 4022 commutator chip, feed "START" pulses to the speech board, introduce spaces between words, and finally to quickly skip past "blanks" on the display. Individually, these one-shots accomplish the following functions:

FF2 triggers the "START" line of the S2A with pulses of appropriate length. Worthy of note is that the "blank detector" operates the "Clear" terminal of FF2 to prevent "START'ing" the S2A when "blanks" occur.

FF3 comes into play when "blanks" occur. Rather than "START'ing" the lengthy cycle of the speech board (data present time cycle) only to get a period of silence for every "blank", FF3 bypasses this cycle and quickly advances the commutator until meaningful information appears on the address lines.

Finally, FF1 introduces a little delay time to permit information on the data lines to stabilize before it is spoken.

As mentioned in 5.2, feedback from either the S2A "BUSY" line or the output of FF3 keeps the system "running", once the user has initiated a cycle by closing the "run" switch. Subsequent opening of the "run" switch allows the "beep" output of the commutator to terminate cycling.

5.1) CD4528 One-Shot Pin Connections and Timing Networks

FF1 and FF2 are on IC13, a 4528 or 4098. FF3 and FF4 are on IC14, another 4528 or 4098. All four one-shots are set up for leading-edge triggering by connecting their "minus TR" terminals to plus 5V (pins 5 and 11 of IC13; pins 5 and 11 of IC14). Triggering is done by using the "plus TR" terminals (pin 4 and pin 12 of each chip).

The "Clear" terminals of FF1, FF3 and FF4 are are all tied to plus 5V (pin 3 of IC13; pins 3 and 13 of IC14). As shown in 3.1.3, the output of the "blank detector" (pin 1 of IC11) goes to the "clear" of FF2 (pin 13 of IC13).

All four one-shots have their "Rx/Cx" terminals going through a resistor to plus 5V; timing capacitors go from their "Rx/Cx" to "Cx". These connections are individually listed below;

Pin 2 of FF1 (IC13) goes through 1 meg to plus 5V, and pin 2 also goes through .003uF to pin 1.

Pin 14 of FF2 (IC13) goes through 470K to plus 5V, and pin 14 also goes .003uF to pin 15.

Pin 2 of FF3 (IC14) goes through 470K to plus 5V, and pin 2 also goes through .003uF to pin 1.

Pin 14 of FF4 (IC14) goes through 3.9K in series with a 1 meg rheostat (word rate control) to plus 5V, and pin 14 also goes through 2.2uF to pin 15.

5.2) One-Shot Interconnections

A 3-input NOR gate whose output triggers FF1 and also "clocks" the 4022 commutator, gives us three inputs into which initiating and feedback pulses can be introduced into the system of one- shots. One of these inputs receives the "run" and "terminate" information, both of which are combined in a NAND gate. The other two NOR inputs receive pulses from two independent feedback loops, one via the speech board and the other from the "Blank advance" one-shot (FF3).

FF1 triggers FF2 which "STARTs" the S2A. When it is finished, the S2A "BUSY" line trips FF4 which inserts a space after the word. FF4 then operates an input to the 3-input NOR gate, causing the system of one-shots to "cycle" again.

For the second feedback loop, FF3, which is also triggered by FF1, is constantly producing pulses at its output; the "blank detector" operates another gate which allows these pulses to reach the remaining input to the one- shot system. Lastly, the "blank detector" "Clears" FF2, thus preventing the speech board from being "START'ed".

5.2.1) "Run" and "Terminate" Circuits

The "run" switch (SPST, either 2-position or momentary) grounds the pin 9 input of a NAND gate (IC7, 4011; pins 8 and 9 in, pin 10 out). This pin 9 input also goes through a 47K pull-up resistor to plus 5V. (Closing the switch brings pin 9 to a logic "0" and initiates "run".)

The pin 8 input of this NAND gate goes to the "7" output of the 4022 (pin 10 of IC4). (This "7" output terminates a "run" if the switch is open.)

The output of the above NAND gate (pin 10 of IC7) goes through an inverter to the 3-input NOR gate at the input; pin 10 of IC7 goes to the inverter input (pin 8 of IC12, the single inverter in the CD4000 NOR gate chip), with the inverter's output (pin 9) going to the pin 13 input of the NOR gate (in the same IC12 chip).

5.2.2)Regenerating Inputs

One of the inputs to the 3-input NOR gate (pin 12 of IC12) goes to the Q output of FF4 (pin 10 of IC14).

The remaining NOR gate input (pin 11) goes to the output of another NOR gate (pin 6 of IC12). The pin 5 input of this latter NOR gate is grounded and is not used. Another input to this NOR (pin 4) comes from the output of the "blank detector" NAND gate (pin 1 of IC11). Finally, the pin 3 NOR input goes to the Q bar output of FF3 (pin 7 of IC14).

5.2.3) One-Shot Arrangement

The output of the 3-input NOR gate (pin 10 of IC12) goes directly to the trigger terminal of the commutator (pin 14 of IC4, triggers on leading edge). This NOR gate's output also triggers FF1 (pin 4 of IC13).

The Q bar output of FF1 (pin 7 of IC13) triggers FF2 (pin 12 of IC13), and the Q output of FF2 (pin 10) goes to the "START" terminal of the S2A pin 6.

Q bar of FF1 also goes to the trigger of FF3 (pin 4 of IC14). As mentioned in 5.2.2, Q bar of FF3 (pin 7 of IC 14) is combined with the "blank detector" by going to pin 3 of a NOR gate on IC12.

As stated in 3.3, the "BUSY" (pin D) goes through a 1N914 diode (anode toward pin D), then through a 10K resistor to ground. The junction of the diode cathode and the resistor goes to the trigger input of FF4 (pin 12 of IC14). As mentioned in 5.2.2, the Q output of FF4 (pin 10) goes to an input of the 3-input NOR gate (pin 12 of IC12).

(6.0) 7107 Voltmeter Chip

(An evaluation kit containing printed circuit board and visual display is available from Jameco *, ICL7107EV/Kit.)

Although this device has versatility which allows widely varying circuit designs (such as a way to avoid using a split power supply), we will consider only the most straight-forward arrangement.

Heat caused by driving the lamps is discipated more effectively in the ceramic version, and the resultant measurement accuracy in these units is better. However, since we are not driving lamps, the low-cost plastic package will do fine.

This device has a differential input whose common-mode voltage may be taken from minus 4 V to plus 4.5 V. These inputs should not be permitted to float--for example if they are used to measure the voltage at the center of a Wheatstone bridge, one end of the bridge should be referenced to "analog common". An "auto zeroing" phase occurs during which the common-mode voltage is taken into consideration and stored in a capacitor (auto zero cap).

A-to-D conversion is accomplished by measuring a ratio between the time taken for an integrator to reach a reference voltage, and the time taken in a de-integration phase. These processes are orchestrated by a clock oscillator inside the chip. This oscillator requires external components to determine its frequency.

Pull-up resistors must be substituted for the lamps--however, these may be comparatively high value, perhaps 47K.

6.1) Terminology Clarification

Strictly for clarification the following two aspects of the chip will be described:

The clock oscillator is made up of two inverters in cascade. Positive feedback is provided by connecting a capacitor from the input of the first to the output of the second, and a resistor across the first inverter causes a reduction of gain within the loop. The reader will note that these components are associated with pins 38, 39 and 40.

A buffered version of the unknown signal is available on the "BUF" pin (28). A resistor in series with this pin charges an "integrator cap" going to "INT" (pin 27). In the same way, the "auto zero" feature is accomplished by storing the common-mode component of the input voltage on the capacitor going from this resistor to A/Z (pin 29).

6.2) Circuit Description

Pin 21 is grounded, pin 1 goes to plus 5V, and pin 26 goes to minus 5V. The lamp test pin (pin 37) goes through 500 ohms to ground and to pin 21. Between C ref plus and C ref minus (pins 34 and 33), is connected a .1 uF capacitor.

Pin 40 goes through 100K to pin 39; pin 40 also goes through 100 pF to pin 38. (This gives us an oscillator frequency of 48 KHz.)

"Reference Low" and "Analog Common" (Pins 35 and 32) are tied together. Reference low also goes to the bottom of a POT, with the top of this POT going through a resistor to plus 5V. (See 6.2.1 and 6.2.2 for values.)

A resistor (See 6.2.1 and 6.2.2 for values) goes from "BUF" (pin 28) to the junction of two capacitors--the "auto zero" cap goes from this junction to "A/Z" (pin 29), and an integrator goes from this junction to "INT" (pin 27) (.22 uF).

For a single-ended input, "Input- low" is grounded. The high and low inputs are shunted by .01 uF, and 1 Meg is placed in series with "input-high".

6.2.1) Plus/Minus 200mV

The reference POT is 1K, and its series resistor is 22K. The POT is to be adjusted to develop 100mV between reference-high and reference-low.

The "BUF" output resistor is 47K, and the "auto zero" cap is .47uF.

6.2.2) Plus/Minus 2V Range

The reference POT is 25K, and its series resistor is 24K. This POT is to be adjusted to develop 1V between reference high and low.

The resistor off the "BUF" output is 470K, and the "auto zero" cap is .047uF.

6.2.3)Pin Connections ICL7107CPL

Note that decimal points are not presented as outputs of this chip, these must be gotten from range-switching circuitry in preceeding circuits.

  • Pin 1--V plus
  • Pin 21--Ground
  • Pin 26--V minus
  • Pin 2--d (ones)
  • Pin 3--c (ones)
  • Pin 4--b (ones)
  • Pin 5--a (ones)
  • Pin 6--f (ones)
  • Pin 7--g (ones)
  • Pin 8--e (ones)
  • Pin 9--d (tens)
  • Pin 10--c (tens)
  • Pin 11--b (tens)
  • Pin 12--a (tens)
  • Pin 13--f (tens)
  • Pin 25--g (tens)
  • Pin 15--d (hundreds)
  • Pin 16--b (hundreds)
  • Pin 17--f (hundreds)
  • Pin 18--e (hundreds)
  • Pin 22--g (hundreds)
  • Pin 23--a (hundreds)
  • Pin 24--c (hundreds)
  • Pin 19--"one" (thousands)
  • Pin 20--"minus"
  • Pin 27--"INT"
  • Pin 28--"BUF"
  • Pin 29--A/Z
  • Pin 30--input low
  • Pin 31--input high
  • Pin 32--analog common (tied to reference low, pin 35)
  • Pin 33--C ref minus
  • Pin 34--C ref plus
  • Pin 35--ref low
  • Pin 36--ref high
  • Pin 37--lamp test
  • Pin 38--osc3
  • Pin 39--osc2
  • Pin 40--osc1

Talk Box Parts List

(Components around 7107 voltmeter chip are not included in this list.)

  • IC's 1,2 and 3--MM74C915
  • IC4--CD4022
  • IC's 5 and 6--CD4069
  • IC's 7 and 8--CD4011
  • IC's 9 and 10--CD4503
  • IC11--CD4012
  • IC12--CD4000
  • IC's 13 and 14--CD4098 or CD4528
  • IC15--LM386
  • IC16--uA7805
  • IC17--uA7908
  • IC18--uA7905
  • IC19--ICL7107CPL
  • IC20--S2A
  • 1--1N914
  • 5--10 K 1/4 watt
  • 2--18 K 1/4 watt
  • 1--47 K 1/4 watt
  • 1--10 K volume control
  • 1--.005uF
  • 3--.01uF
  • 1--.02uF
  • Several--.1uf (bypass capacitors)
  • 1--.22uF
  • Several--25uF 10V (bypassing)
  • 3--250uF 25V


  • Fordham Radio, 855 Conklin Street Farmingdale NY 11735; Phone (800) 645- 9518
  • Jameco Electronics, 1355 Shoreway Road, Belmont CA 94002; Phone (415) 592-8097


by Bob Gunderson, W2JIO

An attempt to answer some of the questions concerning charge-discharge characteristics of the well-known nicads. How often have you had a cell go bad when you least expect it?

Sealed nickel-cadmium cells of the type used in small transistor radios, tape recorders, portable transceivers, power tools, etc. are completely sealed units which provide long life. They are rechargable, and under proper operating conditions, they may be recycled (charged and discharged) many times. Manufacturers of nicads state that the cells may be left in a charged, discharged, or in-between condition without harmful effects for long periods of time.

Here at W2JIO, nickel-cadmium cells have been in use for a long time, and some of the cells have held up for long periods; others have failed rather quickly, and others have lost ampere- hour capacity for one reason or another. To be sure, the nicad represents a significant break-through in electronics technology; however, they are not without their faults, and they do require special maintenance. I have decided to write the following material, with the hope that the information will enable you to use your nickel-cadmium systems with greater success with regard to long and trouble-free service.

Cleaning battery terminals

While these cells are permanently sealed, they are vented to allow gases to escape during charging, and this gassing does bring small amounts of electrolyte, if it is excessive. Then too, small amounts of active material will migrate through the metallic terminals and deposit on the outer surfaces. Thus, in the case of cells, it is wise to remove them from their holders perhaps once each three months and clean both the cell terminals and the holder with ordinary household ammonia. Make certain that the terminals are thoroughly dry before placing the unit back in service. Of course, in the case of a battery, (which is a group of cells connected in series, parallel, or series-parallel), the complete assembly is sealed in a container, and the negative and positive terminals are brought to the outside of the case. There will generally be no migration of electrolyte to the terminals of a battery.


As with all electro- chemical battery systems, operation of the cells produces gassing, and the cell must be vented to allow these gases to escape. (The chemistry of sealed nicads is such that a small amount of gassing can be tolerated inside the cell by the mechanism of chemical recombination). In the sealed nickel-cadmium cell, a small vent in provided in the positive terminal through which excess gases may flow during the charging cycle. It is arranged to open under pressure only, and is closed during normal discharging. Thus, if you make soldered connections to a cell, be very careful not to fill the vent with solder. Should this occur, the cell will more than likely burst, particularly if the charging current is higher than normal. (Manufacturers universally recommend that soldering not be done directly to cell terminals-- solder tabs are often available to isolate the cells from direct heat of the soldering iron).

A number of articles have appeared in the literature discribing various methods of reactivating nicads which are completely discharged, and which will not accept charge. Further, many cells often go into reverse polarity, which means that the positive terminal goes negative, and the original outer (negative) terminal is now positive. In the case of cells which are completely dead, I find that they have often developed internal short circuits, and that they generally cannot be restored. The restoration consists of "zapping" the cells with a high current pulse for less than a second. The idea is that the cell will somehow be freed of its short, and return to normal. On occasion this has worked for me; however, I find that the majority of "zapped" cells will take a charge, but they soon lose their charge once they are allowed to sit on the shelf for a short time. It appears that the leakage path still exists and that the high current pulse has made a slight improvement; but the improvement is short lived. In general, I find that the best cure for these defective cells is a new one, with the older unit placed in the circular file.

If you make the current pulse too long in an effort to completely free the short circuit, you wind up with a battery which holds charge, but the cell exhibits a very high internal impedence. The high current has undoubtedly burned away too much of the active electrode surfaces within the cell. A cell with reversed polarity is another case. Here the active material can generally get reset by charging for a few seconds at a high current, perhaps 10 times the cell's ampere-hour capacity, and then checking with the voltmeter to see if the correct polarity has been reestablished. If it has, the cell may then be charged at its normal rate to bring it back to useful service life.

It is quite common to find a battery with one or more bad cells--either reversed or shorted. In the case of a cell reversal, the high charge pulse will generally set it right; in the case of the shorted-circuited cell, it may be removed, and then replaced with a new cell if possible. The connections to individual cells are generally in the form of metal tabs, welded to the terminals. In replacing the individual cells, I find that the best way to make the new connection is to cut the tab, and then to make soldered connections to the tab rather than to the cell terminal to prevent clogging the vent valve. In a series-connected group of cells making up a battery, the cells must obviously be charged in series. If one particular cell has been discharged to the point of reversing its polarity, it is quite likely that the remaining cells and the charging source will act to force a current through this cell in the wrong direction to provide the reversed polarity effect. Continued charging will make this condition worse. Therefore, if you have a device using a number of cells in series as, for example, your two meter transceiver or handi-talkie, you should check the cells one at a time, making sure that the polarity on each cell is correct. The no load voltage of the cells should be 1.2 to 1.25 volts, although this voltage will be higher when the cells are first removed from the charger. This voltage check should also be made with a load resistance connected to each cell, and if the voltage of a particular cell, under load, is less than perhaps 1.0 volts, it would be well to charge this one unit separately, or fast charge it for a few seconds to get its voltage up to that of the others.

There are several ways to deliver a high current pulse to a defective cell if you want to try reactivating your units. I take the cell and connect it to the 12-volt storage battery for just an instant--less than a second--to deliver a high current pulse. You may also charge a large capacitor (1,000mF or larger), to 5 or 10 volts and then discharge it (with the positive terminal connected to the positive terminal of the cell and the negative to the cell's negative terminal). As mentioned earlier, it is well to charge the cell at the normal rate following this treatment. When the charging is completed, check the cell under load, and if the voltage is below normal, you have a cell with a high internal resistance. This one should then be discarded, since connecting in series with a group of cells will limit the current through the entire battery, reducing the current capacity of the system.

Charge and Discharge Rates

There are several good rules to be followed when charging nicads. Charge and discharge rates are expressed in terms of the C or ampere/rate. This means that if you discharge a 1 ampere hour cell at its C rate, its energy will be expended (it will be discharged in one hour). If it is discharged at the 0.1 C rate, the discharge time is, of course 10 hours, It will be discharged in ten minutes at the 6 C rate.

Trickle Charge

The trickle charging rate is generally taken at 0.01 to 0.03 of the C rate. Thus the trickle charging rate for a 1 ampere hour cell will be from 0.01 to 0.03 amperes, or from 10 to 30 milliamperes. This rate will not recharge the battery to any extent, but it will maintain the charged battery in its charged condition.

Slow or Overnight Charge

This rate of charge is any value from 0.05 C to 0.1 C, and this is the normal rate at which cells are charged.

Quick Charge

This rate is from 0.2 to 0.5 C. At a rate of 0.5 C, this means that the total capacity will be put into the battery in two hours. Actually, the effeciency of the cells is not 100%, so that an additional 30% to 40% of the charging time must be added to bring the battery to full charge.

Fast Charge

This rate extends from the C rate up to perhaps 2 to 3 times this C rate. This means that at the C rate the cell will be charged for one hour; at 2 C, 30 minutes; and at 3 C 20 minutes. At these high rates, however, it is well to watch the battery to see that it doesn't become warm;if it does, terminate the charge until the cell cools, after which time it may be continued. I have found that charging at the 3C rate also helps to free cells which have become defective due to a high resistance leak. It might be well to try this approach to shorted cells before pulsing them with high current.

Storage of Nicads Versus Time and Temperature

A cell stored 0 degrees centigrade (or 32 degrees Fahrenheit), will have about 90% of its full charge at the end of four months or 120 days. At 20 degrees centigrade, there is 80% of the total charge at the end of 20 days, 60% and the end of 40 days, 40% at the end of 60 days, and the total remaing charge is only about 15% after 120 days (only four months). At 50 degrees centigrade, the charge will be down to 50% in 20 days, and all of its charge at the end of 50 days. Therefore, it is obvious that nicads like cooler temperatures. At room temperature, the loss is about 2% per day. The cell will lose about 4% to 5% of its charge per day at 100 degrees Fahrenheit. At 30 degrees Fahrenheit, the loss is about 1.5% per day.

Checking the Ampere-Hour Capacity of Cells and Batteries

This test set up consists of connecting the cell or battery, the load resistor and a DC voltmeter all in parallel. In order to calculate the load resistance necessary to discharge the battery at its C rate, RL equals the battery's voltage divided by the ampere hour capacity.

Examples of this test set up might be a 5 ampere-hour battery rated at ten cells, or 12.5 volts. The value of RL would be 12.5 over 5 or 2.5 ohms. The wattage consumed by this value of load resistance would be the square of the voltage divided by the resistance, or 12.5 squared, or 156.25, divided by 2.5, or 62.5 watts. The load resistance for a one ampere-hour cell would 1.25 over 1 or 1.25 ohms and the wattage would be 1.25 watts.

Bring the battery to a full charge and allow it to settle for several hours after the charge has been terminated. Connect the battery into the test circuit and measure the time it takes to discharge the battery to 1 volt per cell. If the time is one hour or more, the battery is delivering its rated capacity. If the discharge time is less than the rated value, use the following: measure time in minutes over 60 times the rated capacity in ampere-hours, equals the actual capacity. For example, suppose your 1.25 volt cell, rated at 1 ampere-hour delivers its rated load for only 45 minutes or 45 over 60 of the rated time. The ampere-hour capacity of this cell will be only 0.75 ampere- hours. If this is the case, recycle the battery through its charge and discharge cycles three or four times, after which time the ampere-hour capacity should be returned to normal since this will remove any memory set which may have occured. Under no circumstances should you allow the cell voltage to go below 1.0 volts during this ampere-hour capacity test.

Cell Polarity Reversal--If you have a cell which produces an open circuit voltage of less than 1.0 volts, or if the cell exhibits a reversed polarity, (positive terminal is negative and negative terminal is positive) as indicated by your voltmeter (DC), the cell may be permanently damaged. As mentioned earlier, you can subject the cell to a large current pulse for a short period, or you may connect the cell to a charging source, and charge the cell at the C 10 rate, or ten times the cell capacity. This means that if you have a 1 ampere-hour cell, you would charge it at 10 amps for just 1 hour; a 500mAH cell would be charged at the 5 ampere rate for 1 hour, etc. When making this test, check the cell carefully to see that it does not become warm. If it does, terminate the experiment. However, you might measure the terminal voltage, and if the cell has taken a charge, the terminal voltage will be higher than 1.2-1.25 volts. If it is not, the cell may be considered useless, and should be discarded. This C 10 rate should never be used on cells which are good as this will cause considerable heating and will more likely produce permanent damage to the cell.

Fast Chargers

Modern communications equipment is made available with two types of battery chargers; the slow charger in which the cells are charged at the 0.1 C rate for 14 to 16 hours and the so-called "fast charge" in which the cell is charged at perhaps 3 times the normal slow charge rate for 3 or 4 hours. I have found that this 10 C rate is hard on the smaller cells, and prefer 3 to 5 C for this rough charge with these cells.

Battery Chargers

The manufacturers recommend that nickel- cadmium cells be charged from a constant current source. This means that the charging voltage is quite high and the current for the cells is limited by a rather large series resistance connected between the source of DC and the battery or cell. It is obvious that with this arrangement, all cells are charged in series--never in parallel, so that the charging current is equal in all parts of the series circuit and therefore, equal in all series-connected cells. Of course, the one major disadvantage of this system is the fact that there is no simple means of checking the condition of the individual cells during the charging cycle, particularly when all cells are mounted in a common container or holder.

Jim Swail, VE3KF suggested that the cells could be charged in parallel, with each cell isolated from the others by means of a silicon diode and its own series resistor. A common, high-current transformer is used, with each cell fed by its own half-wave rectifier (a single diode) in series with its own current limiting resistance to provide the constant current source. In other words, we have a common power supply which produces a number of constant current sources--one for each cell. The common negatives of the cells are connected together and then connected to the common side of the transformer secondary. I have been using this approach for some time, and it appears to work very well. With each cell mounted in its own holder, you can check the voltage developed across its terminals during the charging cycle, or you can measure the current through the cell by measuring the voltage across the current limiting resistance, and then use Ohm's law to determine the current.

David Heavner, W2USQ, came up with an interesting idea for a battery charger, employing the small transformers used by the telephone company for the lights in the telephones. These transformers are available in various voltages from 6-8 to 18-24 and they plug directly into the AC outlet. The connections to the low voltage secondary are made to two terminal screws on the body of the transformer. The rectifier and current limiting resistor may be built into your battery-powered instrument, with a jack to accept a plug from the transformer secondary. You may disconnect the battery from the internal circuitry of the instrument when charging to prevent the application of too high a voltage to the circuits, and this can be done with a switch or with a multi-circuit jack. I use this arrangement with rechargable 9- volt nickel-cadmium batteries and with the type AA pen light battery configurations with great success.

Pulse Charging Heading

There are some newer charging arrangements which use a pulsed-source of DC to charge the cells. By this means, the charging current is large, but delivered to the cell for a fraction of a second. This shortens the duty cycle, and allows the cell to cool (to rest) during the time when the cell is off. Pulsed-charging is catching on rapidly; however, I would think the slow 0.1 C rate would be most satisfactory for long battery life.

CORRECTION - "SCA Decoder" (SKTF, Fall 1981)

We forgot to power the RCA CA3089; pin 11 goes to the VCC line, which in turn goes through a switch to the power supply.


by Richard Oehm, KB6TC

[Editor's note: A correction to this article was published in a later issue. Please click here to read this correction.]

SCA (Subsidiary Communications Authorization) is a technique used by many FM radio stations to broadcast closed-circuit additional programs without interfering with normal open- channel broadcasting. The additional programs cannot be heard with a standard FM broadcast receiver unless special circuitry of the type described in this article is used to decode them. (Besides radio reading services, SCA broadcasts include uninterrupted background music, MUZAK, ethnic and religious programs, special news and weather broadcasts, etc.)

SCA transmission is made by frequency modulation of a supersonic (usually 67 KHz) tone and superimposing this signal onto the open-channel broadcast as a subcarrier.

Reception of SCA is accomplished by filtering the subcarrier out from the regular programming, then limiting it to remove any amplitude variations, and finally FM detecting the subcarrier to extract its information.

The circuit to be described is designed around the RCA CA3089 FM IF system, which is packaged in a 16-pin DIP chip. It is intended to be connected to the output of the detector in an FM receiver. Filtering out the subcarrier is done with RLC tuned circuits; amplifying and limiting is done within the integrated circuit.

Next, using an external phase shift network, the integrated circuit detects the subcarrier. The chip contains a high-level audio amplifier/buffer which provides a low-output impedence.

The output of the receiver detector is applied through C12 to a Darlington amplifier made up of Q1 and Q2. R7 and R8 provide a DC bias for the Darlington circuit, while R6 provides DC feedback to maintain stability. R5 and C13 determine the amount of feedback at 67 KHz and thus determine the gain of the amplifier stage.

L3 and C11 provide a tuned-load for the amplifier stage; this bandpass filter rejects signals and noise above and below 67 KHz. R4, shunted across L3 and C11, controls the bandwidth of this tuned circuit. L10 and C2 form another tuned circuit to increase the rejection of noise, and R3 controls its bandwidth. C7 and C8 provide a signal ground for this latter tuned circuit, while permitting internal DC biasing of the integrated circuit.

Audio from the integrated circuit is de-emphasized by the network of R2 and C2 (a time constant of 150 uSec.). C3 removes the DC component from the output signal. C15 was empiracally chosen to provide for extra filtering of hiss and cross-talk.

Circuit Description

The negative end of the supply is grounded, as are pins 4,5 and 14 of the IC. Also at ground are the cold return connections of both input and output. The positive supply (from 7 to 15 volts) goes through an on/off switch to the plus V line (VCC), with this line being bypassed to ground by the parallel combination of C5 and C14 (.1uF and 10uF, respectively, with the negative side of C14 being grounded).

The hot input terminal goes through C12 (330 pF) to the base of Q1; this base also goes through R8 (27K) to VCC, and through R7 (120K) to ground. The emitter of Q1 goes to the base of Q2. (Both Q1 and Q2 are 2N2222.) The collectors of Q1 and Q2 are connected together. The emitter of Q2 goes through R6 (680 ohms) to ground, and this emitter also goes through R5 in series with C13 to ground (100 ohms and .01uF, respectively).

The Q1-Q2 collectors go to one end of a parallel tuned circuit made up of L3, C11 and R4 (1000uH, 5600pF, and 2.2K, respectively) the other end of this tuned circuit goes to VCC. These collectors go through C10 (430pF) to pin 1 of the IC, its input.

Pin 1 goes through another parallel tuned circuit to pin 3, with this tuned circuit consisting of C9,L2, and R3 (5600pF, 1000uH and 2.2K, respectively). Pin 3 goes through C7 (.1uF) to ground, and pin 2 goes through C8 (.1uF) to pin 3. Pin 8 goes through C6 (120pF) to pin 9. Pin 9 goes through another parallel RLC circuit to pin 10, with this parallel combination consisting of R1, L1, C4, and C1 (22K, 10mH, 390pF, and a 16-150pF trimmer, respectively).

Pin 5 of the IC is a squelch input and is grounded. Pin 6, the output of the IC, goes through R2 (15K), then through C2 (.01uF) to ground. The junction of R2 and C2 goes through C3 (.1uF) to the output. The output is shunted by C15 (.22uF).

Pin 13 is a signal level output which could be used to operate a squelch; it has not been used in this circuit. Pins 12, 15, and 16 have no connection. Pin 7 is a test point (see text).



  • C1--16-150pF trimmer
  • C2,C13--.01uF disc
  • C3,C7,C8--.1uF disc
  • C4--390pF 5% (mica)
  • C5--.1uF disc
  • C6--120pF 5%
  • C14--10uF electrolytic 25V
  • C9,C11--5600pF 5% (mica)
  • C10--430pF 5%
  • C12--330pF disc
  • C15--.22uF disc


  • L1--10mH 10%
  • L2,L3--1000uH 5%


  • IC1--RCA CA3089-E or TCA3089
  • Q1,Q2--2N2222

Resistors (1/4 watt, 5%):

  • R1--22K
  • R2--15K
  • R3,R4--22K
  • R5--100 ohms
  • R6--680 ohms
  • R7--120K
  • R8--27K

The constructed unit may be mounted within the FM receiver cabinet, or you may wish to house it separately in its own cabinet. All connections should be made with shielded audio cable.

This SCA demultiplexer must be connected to a power source capable of delivering 7 to 15V, 30mA. The audio output is approximately .5V RMS, which should be enough to drive most amplifiers.

The demultiplexer's input is connected to the output of the FM receiver detector just prior to de- emphasis. This point is often referred to as "composite out", and it may even be available from a jack on the rear of the receiver cabinet. (This jack may also be labeled detector out or output to mpx adaptor.) In the case of a stereo receiver where there is no such jack, the input connection is made between the detector and the stereo decoder.

After all connections have been made and power is applied, tune your receiver from station to station. If a station is not broadcasting SCA, noise and distorted main-channel audio will be heard. When, however, a station broadcasting SCA is received, the SCA program will be heard clearly. If a high impedence voltmeter is available, connect it between the test point (pin 7) and pin 10 of the IC, and adjust C1 for 0 volts. If a voltmeter is not available, simply adjust C1 for the least distortion of the SCA program. Once adjusted, C1 should not need readjustment, even if the demultiplexer is used on another FM receiver.

It should be noted that the quality of the SCA signal is largely a function of the broadcast quality and the quality of the FM receiver. Although slight phase non-linearity within the FM receiver may not affect stereo reception, it will appear as cross-talk from the main channel to the SCA channel. Cross-talk will be minimized by carefully tuning the receiver's station selector and by using a good antenna. For good SCA reception, the signal must be strong and free of multipath distortion. In my experience, the sound quality of SCA programming with this circuit is far better than that obtained from commercially-made SCA receivers.

The circuit described in this article may be purchased as a kit with a printed circuit board, or as an assembled unit from my company, Metcom. Also available from Metcom is a high quality AM/FM/SCA portable battery operated radio with this demultiplexer built in. For more information about the radio or the SCA decoder circuit, please write to Metcom, 524 Kendall Ave, Number 3, Palo Alto, CA 94306, or call Metcom at (415) 494-8801. If you telephone, please ask for Richard Oehm.

Metcom plans to go into production on other items, such as a VU meter, and their availability will be announced in the future.


Another product of the fertile mind of David Plumlee is this column. Its concept is dear to my heart, and there is no doubt we shall all benefit in some way from the exchange of ideas between our readers. Space is a premium!--please make your entries short and sweet.

Those wishing to discuss digital electronics or share ideas on electronic generation of music, contact David Plumlee, 1625 Harris, Independence MO 64052.

Talk programs are available for the Radio Shack computers (TRS-80; model I level II) with its accompanying "Voice Synthesizer". Two such programs can be gotten from Mike Cozzolino, 4536 Edison Ave., Sacramento CA 95821. You must supply the computer-grade casettes.

TRS-80 (model I, level I) and Apple II computer manuals are available on tape (to be supplied by you) from Eric Clegg, 1801 Kennedy Blvd. Apt 2105, Philadelphia PA 19103.

Also Eric Clegg (see above) is willing to make code practice tapes using his AKB I microlog keyboard. Please contact him at the above address.

Aiming at publishing a "call book" of blind hams, the ACB Service Network is collaborating with the Radio Reading Service of Oklahoma City. To register your call sign, name, and address, write to Travis Harris, P.O. Box 25352, Oklahoma City OK 73125.

Editor's Note

Regarding the call book, it is more than just fun to have a call book of blind amateurs. Those of us close to the field of aids and appliances see stumbling blocks and hear complaints from two sides: on the one hand, industry shies away from making specialized equipment on the basis that the market is small, and when devices are actually produced, their costs must high. On the other hand, blind and handicapped people who cannot afford these high cost devices, are rarely in a position to demonstrate to the mainstream of society that a market for these devices would exist if they were affordable. A call book presents one chance for collecting a lump of data suggesting that a reasonable number of us are favorable to the promise of technology. For the benefit of those who work in the field of sensory aids, and for those who use them, please register as indicated above.


Before one can accomplish anything in technical fields of endeavor, one needs the basic tools of the trade, fabrication techniques and test instruments. The principles of both aspects have been presented in these first five issues of the Smith- Kettlewell Technical File. What follows?:

Beginners take heart! A new column called "lexicography" will list books and study materials which now exist and as they become available. Also beginners' projects will start appearing so as to gently escort those who have been lost in the past into the world of tinkering. Tape cassettes steering beginners through project layout and construction details of instruments already presented will be made available as supplemental material on request.

Adaptive test equipment will always be with us, and items such as the auditory oscilloscope will be presented here along with finishing our discussion of VU meters.

Now that we have gotten "tools of the trade" out of the way, it's time to have some fun! In additon to light probes, sound beacons, simple receivers and musical instruments, a hands-free auditory compass that goes "beep beep" for north and "ding ding" for south has been designed by Al Alden here at Smith- Kettlewell, and no sailor or tiller of the field should be without one.

Nicholas Kovak of Somerset N.J. requested that we do an article on dimensions of screws in the metric system. I would like to expand this article to include information on the styles of screw heads, thread sizes of commonly used screws in both English and metric systems, and hardware sources from which these items are available. I am not fully qualified to write this paper myself--any volunteers?

One topic for certain to be covered this next year is splicing and editing of audio tape, including the repair of casettes.

Seasons greetings and good experimenting to all of you. To those whose projects are not yet functioning, I offer my favorite consolation, "IF the good Lord had wanted electricity to flow, He'd have made wire hollow."